29 #define QQQdialect MPLABX 43 #undef QQQMULTIPROCESSEXH 46 #define qqqMaxBranchDepth 20 47 #define QQQstructbitmap 59 #undef QQQTEMPLATEONLY 61 #define QQQUPLOADATEND 63 #undef QQQASHLINGVITRA 65 #define qqqbitmapint unsigned int 67 #undef QQQTIC2XSERIALIO 69 #undef QQQCOMPRESSED_EXH 76 #define commands_65zzopen zzopen 78 #define commands_65zqqzqz1 zqqzqz1 81 #define FILEPOINT FILE * f, 82 #if !defined(QQQTEMPLATEONLY) && !defined(FILE) && !defined(QQQNOSTDIO) 98 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port.h" 99 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port_common.h" 102 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port.c" 103 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port_common.c" 111 #if defined(QQQstructbitmap) && defined(QQQSINGLEFILE) 112 #ifndef LDRA_VOID_FUNC 113 #define LDRA_VOID_FUNC 116 #if defined(QQQMAINFL) 139 #ifdef QQQ_KEEPCOMMENTS 147 #if !defined(QQQSUPPRESS_UNDEF) 153 #undef QQQHITMAP_STORAGE 155 #define qqnull_params void 156 #define QQQ_PROTOTYPE_DEF 158 #undef QQ_ANSI_PROTOTYPE 160 #define QQ_ANSI_PROTOTYPE 1 163 #define QQ_ANSI_PROTOTYPE 1 169 #define ELEMENT(N) qqqbitmapint element##N; 171 #include "commands_65zbelem.def" 175 #define ELEMENT(N) 0, 177 #include "commands_65zbelem.def" 257 uint8_t command [ 7 ] ;
258 bool process_complete_flag ;
259 bool b_command_complete_flag ;
260 bool sw_status_bit_check ;
562 const uint8_t Bytes [] ) ;
593 const uint8_t Bytes [] ) ;
709 #ifndef _SYS_DEFINITIONS_H 710 #define _SYS_DEFINITIONS_H 719 #include "system/common/sys_common.h" 720 #include "system/common/sys_module.h" 804 #ifndef _SYSTEM_CONFIG_H 805 #define _SYSTEM_CONFIG_H 824 #define SYS_VERSION_STR "2.06" 825 #define SYS_VERSION 20600 829 #define SYS_CLK_FREQ 200000000ul 830 #define SYS_CLK_BUS_PERIPHERAL_1 100000000ul 831 #define SYS_CLK_BUS_PERIPHERAL_2 100000000ul 832 #define SYS_CLK_BUS_PERIPHERAL_3 100000000ul 833 #define SYS_CLK_BUS_PERIPHERAL_4 100000000ul 834 #define SYS_CLK_BUS_PERIPHERAL_5 100000000ul 835 #define SYS_CLK_BUS_PERIPHERAL_7 200000000ul 836 #define SYS_CLK_BUS_PERIPHERAL_8 100000000ul 837 #define SYS_CLK_CONFIG_PRIMARY_XTAL 0ul 838 #define SYS_CLK_CONFIG_SECONDARY_XTAL 32768ul 840 #define SYS_PORT_A_ANSEL 0x3F00 841 #define SYS_PORT_A_TRIS 0xFFED 842 #define SYS_PORT_A_LAT 0x0010 843 #define SYS_PORT_A_ODC 0x0000 844 #define SYS_PORT_A_CNPU 0x0020 845 #define SYS_PORT_A_CNPD 0x0000 846 #define SYS_PORT_A_CNEN 0x0021 847 #define SYS_PORT_B_ANSEL 0x10C8 848 #define SYS_PORT_B_TRIS 0x91FF 849 #define SYS_PORT_B_LAT 0x0000 850 #define SYS_PORT_B_ODC 0x0000 851 #define SYS_PORT_B_CNPU 0x0000 852 #define SYS_PORT_B_CNPD 0x0000 853 #define SYS_PORT_B_CNEN 0x0000 854 #define SYS_PORT_C_ANSEL 0xCFE1 855 #define SYS_PORT_C_TRIS 0xFFFF 856 #define SYS_PORT_C_LAT 0x0000 857 #define SYS_PORT_C_ODC 0x0000 858 #define SYS_PORT_C_CNPU 0x0000 859 #define SYS_PORT_C_CNPD 0x0000 860 #define SYS_PORT_C_CNEN 0x0000 861 #define SYS_PORT_D_ANSEL 0xC100 862 #define SYS_PORT_D_TRIS 0xFFFF 863 #define SYS_PORT_D_LAT 0x0000 864 #define SYS_PORT_D_ODC 0x0000 865 #define SYS_PORT_D_CNPU 0x0000 866 #define SYS_PORT_D_CNPD 0x0000 867 #define SYS_PORT_D_CNEN 0x0000 868 #define SYS_PORT_E_ANSEL 0xFC00 869 #define SYS_PORT_E_TRIS 0xFDFF 870 #define SYS_PORT_E_LAT 0x0000 871 #define SYS_PORT_E_ODC 0x0000 872 #define SYS_PORT_E_CNPU 0x0000 873 #define SYS_PORT_E_CNPD 0x0000 874 #define SYS_PORT_E_CNEN 0x0000 875 #define SYS_PORT_F_ANSEL 0xCEC0 876 #define SYS_PORT_F_TRIS 0xEFFF 877 #define SYS_PORT_F_LAT 0x0000 878 #define SYS_PORT_F_ODC 0x0000 879 #define SYS_PORT_F_CNPU 0x0000 880 #define SYS_PORT_F_CNPD 0x0000 881 #define SYS_PORT_F_CNEN 0x0000 882 #define SYS_PORT_G_ANSEL 0x8CBC 883 #define SYS_PORT_G_TRIS 0xDFFF 884 #define SYS_PORT_G_LAT 0x0000 885 #define SYS_PORT_G_ODC 0x0000 886 #define SYS_PORT_G_CNPU 0x0000 887 #define SYS_PORT_G_CNPD 0x0000 888 #define SYS_PORT_G_CNEN 0x0000 889 #define SYS_PORT_H_ANSEL 0x0070 890 #define SYS_PORT_H_TRIS 0xB3FB 891 #define SYS_PORT_H_LAT 0x0000 892 #define SYS_PORT_H_ODC 0x0000 893 #define SYS_PORT_H_CNPU 0x0000 894 #define SYS_PORT_H_CNPD 0x0000 895 #define SYS_PORT_H_CNEN 0x0000 896 #define SYS_PORT_J_ANSEL 0x0000 897 #define SYS_PORT_J_TRIS 0x8B7F 898 #define SYS_PORT_J_LAT 0x0080 899 #define SYS_PORT_J_ODC 0x0000 900 #define SYS_PORT_J_CNPU 0x0000 901 #define SYS_PORT_J_CNPD 0x0000 902 #define SYS_PORT_J_CNEN 0x0800 903 #define SYS_PORT_K_ANSEL 0xFF00 904 #define SYS_PORT_K_TRIS 0xFFFF 905 #define SYS_PORT_K_LAT 0x0000 906 #define SYS_PORT_K_ODC 0x0000 907 #define SYS_PORT_K_CNPU 0x0000 908 #define SYS_PORT_K_CNPD 0x0000 909 #define SYS_PORT_K_CNEN 0x0000 913 #define SYS_TMR_POWER_STATE SYS_MODULE_POWER_RUN_FULL 914 #define SYS_TMR_DRIVER_INDEX DRV_TMR_INDEX_0 915 #define SYS_TMR_MAX_CLIENT_OBJECTS 5 916 #define SYS_TMR_FREQUENCY 1000 917 #define SYS_TMR_FREQUENCY_TOLERANCE 10 918 #define SYS_TMR_UNIT_RESOLUTION 10000 919 #define SYS_TMR_CLIENT_TOLERANCE 10 920 #define SYS_TMR_INTERRUPT_NOTIFICATION false 926 #define DRV_IC_DRIVER_MODE_STATIC 929 #define DRV_SPI_NUMBER_OF_MODULES 6 932 #define DRV_SPI_POLLED 1 933 #define DRV_SPI_ISR 0 934 #define DRV_SPI_MASTER 1 935 #define DRV_SPI_SLAVE 0 937 #define DRV_SPI_EBM 1 938 #define DRV_SPI_8BIT 1 939 #define DRV_SPI_16BIT 1 940 #define DRV_SPI_32BIT 0 941 #define DRV_SPI_DMA 0 943 #define DRV_SPI_INSTANCES_NUMBER 3 944 #define DRV_SPI_CLIENTS_NUMBER 3 945 #define DRV_SPI_ELEMENTS_PER_QUEUE 10 947 #define DRV_SPI_SPI_ID_IDX0 SPI_ID_1 948 #define DRV_SPI_TASK_MODE_IDX0 DRV_SPI_TASK_MODE_POLLED 949 #define DRV_SPI_SPI_MODE_IDX0 DRV_SPI_MODE_MASTER 950 #define DRV_SPI_ALLOW_IDLE_RUN_IDX0 false 951 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX0 DRV_SPI_PROTOCOL_TYPE_FRAMED 952 #define DRV_SPI_FRAME_SYNC_PULSE_IDX0 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 953 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX0 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 954 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX0 SPI_FRAME_PULSE_DIRECTION_OUTPUT 955 #define DRV_SPI_FRAME_PULSE_EDGE_IDX0 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 956 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX0 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 957 #define DRV_SPI_COMM_WIDTH_IDX0 SPI_COMMUNICATION_WIDTH_16BITS 958 #define DRV_SPI_CLOCK_SOURCE_IDX0 SPI_BAUD_RATE_PBCLK_CLOCK 959 #define DRV_SPI_SPI_CLOCK_IDX0 CLK_BUS_PERIPHERAL_2 960 #define DRV_SPI_BAUD_RATE_IDX0 1000000 961 #define DRV_SPI_BUFFER_TYPE_IDX0 DRV_SPI_BUFFER_TYPE_ENHANCED 962 #define DRV_SPI_CLOCK_MODE_IDX0 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 963 #define DRV_SPI_INPUT_PHASE_IDX0 SPI_INPUT_SAMPLING_PHASE_IN_MIDDLE 964 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX0 0xFFFF 965 #define DRV_SPI_QUEUE_SIZE_IDX0 10 966 #define DRV_SPI_RESERVED_JOB_IDX0 1 968 #define DRV_SPI_SPI_ID_IDX1 SPI_ID_2 969 #define DRV_SPI_TASK_MODE_IDX1 DRV_SPI_TASK_MODE_POLLED 970 #define DRV_SPI_SPI_MODE_IDX1 DRV_SPI_MODE_MASTER 971 #define DRV_SPI_ALLOW_IDLE_RUN_IDX1 false 972 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX1 DRV_SPI_PROTOCOL_TYPE_FRAMED 973 #define DRV_SPI_FRAME_SYNC_PULSE_IDX1 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 974 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX1 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 975 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX1 SPI_FRAME_PULSE_DIRECTION_OUTPUT 976 #define DRV_SPI_FRAME_PULSE_EDGE_IDX1 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 977 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX1 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 978 #define DRV_SPI_COMM_WIDTH_IDX1 SPI_COMMUNICATION_WIDTH_8BITS 979 #define DRV_SPI_CLOCK_SOURCE_IDX1 SPI_BAUD_RATE_PBCLK_CLOCK 980 #define DRV_SPI_SPI_CLOCK_IDX1 CLK_BUS_PERIPHERAL_2 981 #define DRV_SPI_BAUD_RATE_IDX1 1000000 982 #define DRV_SPI_BUFFER_TYPE_IDX1 DRV_SPI_BUFFER_TYPE_ENHANCED 983 #define DRV_SPI_CLOCK_MODE_IDX1 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 984 #define DRV_SPI_INPUT_PHASE_IDX1 SPI_INPUT_SAMPLING_PHASE_IN_MIDDLE 985 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX1 0xFF 986 #define DRV_SPI_QUEUE_SIZE_IDX1 10 987 #define DRV_SPI_RESERVED_JOB_IDX1 1 989 #define DRV_SPI_SPI_ID_IDX2 SPI_ID_4 990 #define DRV_SPI_TASK_MODE_IDX2 DRV_SPI_TASK_MODE_POLLED 991 #define DRV_SPI_SPI_MODE_IDX2 DRV_SPI_MODE_MASTER 992 #define DRV_SPI_ALLOW_IDLE_RUN_IDX2 false 993 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX2 DRV_SPI_PROTOCOL_TYPE_FRAMED 994 #define DRV_SPI_FRAME_SYNC_PULSE_IDX2 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 995 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX2 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 996 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX2 SPI_FRAME_PULSE_DIRECTION_OUTPUT 997 #define DRV_SPI_FRAME_PULSE_EDGE_IDX2 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 998 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX2 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 999 #define DRV_SPI_COMM_WIDTH_IDX2 SPI_COMMUNICATION_WIDTH_16BITS 1000 #define DRV_SPI_CLOCK_SOURCE_IDX2 SPI_BAUD_RATE_PBCLK_CLOCK 1001 #define DRV_SPI_SPI_CLOCK_IDX2 CLK_BUS_PERIPHERAL_2 1002 #define DRV_SPI_BAUD_RATE_IDX2 500000 1003 #define DRV_SPI_BUFFER_TYPE_IDX2 DRV_SPI_BUFFER_TYPE_ENHANCED 1004 #define DRV_SPI_CLOCK_MODE_IDX2 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 1005 #define DRV_SPI_INPUT_PHASE_IDX2 SPI_INPUT_SAMPLING_PHASE_AT_END 1006 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX2 0x0000 1007 #define DRV_SPI_QUEUE_SIZE_IDX2 10 1008 #define DRV_SPI_RESERVED_JOB_IDX2 1 1010 #define DRV_TMR_INTERRUPT_MODE true 1012 #define DRV_TMR_PERIPHERAL_ID_IDX0 TMR_ID_2 1013 #define DRV_TMR_INTERRUPT_SOURCE_IDX0 INT_SOURCE_TIMER_2 1014 #define DRV_TMR_INTERRUPT_VECTOR_IDX0 INT_VECTOR_T2 1015 #define DRV_TMR_ISR_VECTOR_IDX0 _TIMER_2_VECTOR 1016 #define DRV_TMR_INTERRUPT_PRIORITY_IDX0 INT_PRIORITY_LEVEL4 1017 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX0 INT_SUBPRIORITY_LEVEL0 1018 #define DRV_TMR_CLOCK_SOURCE_IDX0 DRV_TMR_CLKSOURCE_INTERNAL 1019 #define DRV_TMR_PRESCALE_IDX0 TMR_PRESCALE_VALUE_8 1020 #define DRV_TMR_OPERATION_MODE_IDX0 DRV_TMR_OPERATION_MODE_16_BIT 1021 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX0 false 1022 #define DRV_TMR_POWER_STATE_IDX0 1023 #define DRV_TMR_PERIPHERAL_ID_IDX1 TMR_ID_7 1024 #define DRV_TMR_INTERRUPT_SOURCE_IDX1 INT_SOURCE_TIMER_7 1025 #define DRV_TMR_INTERRUPT_VECTOR_IDX1 INT_VECTOR_T7 1026 #define DRV_TMR_ISR_VECTOR_IDX1 _TIMER_7_VECTOR 1027 #define DRV_TMR_INTERRUPT_PRIORITY_IDX1 INT_PRIORITY_LEVEL3 1028 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX1 INT_SUBPRIORITY_LEVEL0 1029 #define DRV_TMR_CLOCK_SOURCE_IDX1 DRV_TMR_CLKSOURCE_INTERNAL 1030 #define DRV_TMR_PRESCALE_IDX1 TMR_PRESCALE_VALUE_16 1031 #define DRV_TMR_OPERATION_MODE_IDX1 DRV_TMR_OPERATION_MODE_16_BIT 1032 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX1 false 1033 #define DRV_TMR_POWER_STATE_IDX1 1035 #define DRV_TMR_PERIPHERAL_ID_IDX2 TMR_ID_6 1036 #define DRV_TMR_INTERRUPT_SOURCE_IDX2 INT_SOURCE_TIMER_6 1037 #define DRV_TMR_INTERRUPT_VECTOR_IDX2 INT_VECTOR_T6 1038 #define DRV_TMR_ISR_VECTOR_IDX2 _TIMER_6_VECTOR 1039 #define DRV_TMR_INTERRUPT_PRIORITY_IDX2 INT_PRIORITY_LEVEL1 1040 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX2 INT_SUBPRIORITY_LEVEL0 1041 #define DRV_TMR_CLOCK_SOURCE_IDX2 DRV_TMR_CLKSOURCE_INTERNAL 1042 #define DRV_TMR_PRESCALE_IDX2 TMR_PRESCALE_VALUE_16 1043 #define DRV_TMR_OPERATION_MODE_IDX2 DRV_TMR_OPERATION_MODE_16_BIT 1044 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX2 false 1045 #define DRV_TMR_POWER_STATE_IDX2 1047 #define DRV_TMR_PERIPHERAL_ID_IDX3 TMR_ID_1 1048 #define DRV_TMR_INTERRUPT_SOURCE_IDX3 INT_SOURCE_TIMER_1 1049 #define DRV_TMR_INTERRUPT_VECTOR_IDX3 INT_VECTOR_T1 1050 #define DRV_TMR_ISR_VECTOR_IDX3 _TIMER_1_VECTOR 1051 #define DRV_TMR_INTERRUPT_PRIORITY_IDX3 INT_PRIORITY_LEVEL2 1052 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX3 INT_SUBPRIORITY_LEVEL0 1053 #define DRV_TMR_CLOCK_SOURCE_IDX3 DRV_TMR_CLKSOURCE_INTERNAL 1054 #define DRV_TMR_PRESCALE_IDX3 TMR_PRESCALE_VALUE_256 1055 #define DRV_TMR_OPERATION_MODE_IDX3 DRV_TMR_OPERATION_MODE_16_BIT 1056 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX3 false 1057 #define DRV_TMR_POWER_STATE_IDX3 1059 #define DRV_TMR_PERIPHERAL_ID_IDX4 TMR_ID_3 1060 #define DRV_TMR_INTERRUPT_SOURCE_IDX4 INT_SOURCE_TIMER_3 1061 #define DRV_TMR_INTERRUPT_VECTOR_IDX4 INT_VECTOR_T3 1062 #define DRV_TMR_ISR_VECTOR_IDX4 _TIMER_3_VECTOR 1063 #define DRV_TMR_INTERRUPT_PRIORITY_IDX4 INT_PRIORITY_LEVEL1 1064 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX4 INT_SUBPRIORITY_LEVEL0 1065 #define DRV_TMR_CLOCK_SOURCE_IDX4 DRV_TMR_CLKSOURCE_INTERNAL 1066 #define DRV_TMR_PRESCALE_IDX4 TMR_PRESCALE_VALUE_16 1067 #define DRV_TMR_OPERATION_MODE_IDX4 DRV_TMR_OPERATION_MODE_16_BIT 1068 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX4 false 1069 #define DRV_TMR_POWER_STATE_IDX4 1073 #define DRV_USART_INSTANCES_NUMBER 1 1074 #define DRV_USART_CLIENTS_NUMBER 1 1075 #define DRV_USART_INTERRUPT_MODE false 1076 #define DRV_USART_BYTE_MODEL_SUPPORT true 1077 #define DRV_USART_READ_WRITE_MODEL_SUPPORT false 1078 #define DRV_USART_BUFFER_QUEUE_SUPPORT false 1086 #define DRV_USBHS_DEVICE_SUPPORT true 1088 #define DRV_USBHS_HOST_SUPPORT false 1090 #define DRV_USBHS_INSTANCES_NUMBER 1 1092 #define DRV_USBHS_INTERRUPT_MODE true 1094 #define DRV_USBHS_ENDPOINTS_NUMBER 2 1097 #define USB_DEVICE_DRIVER_INITIALIZE_EXPLICIT 1099 #define USB_DEVICE_INSTANCES_NUMBER 1 1101 #define USB_DEVICE_EP0_BUFFER_SIZE 64 1103 #define USB_DEVICE_ENDPOINT_QUEUE_DEPTH_COMBINED 2 1111 #define LED1Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 1112 #define LED1On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 1113 #define LED1Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 1114 #define LED1StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 1115 #define LED1StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 , Value ) 1117 #define LED2Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 1118 #define LED2On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 1119 #define LED2Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 1120 #define LED2StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 1121 #define LED2StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 , Value ) 1123 #define DMP_FIRE_LEDToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 1124 #define DMP_FIRE_LEDOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 1125 #define DMP_FIRE_LEDOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 1126 #define DMP_FIRE_LEDStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 1127 #define DMP_FIRE_LEDStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 , Value ) 1129 #define HVPS_ENBToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 1130 #define HVPS_ENBOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 1131 #define HVPS_ENBOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 1132 #define HVPS_ENBStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 1133 #define HVPS_ENBStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 , Value ) 1135 #define RLY_HVPS_OUTToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 1136 #define RLY_HVPS_OUTOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 1137 #define RLY_HVPS_OUTOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 1138 #define RLY_HVPS_OUTStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 1139 #define RLY_HVPS_OUTStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 , Value ) 1141 #define RLY_WL_SPS_POLToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 1142 #define RLY_WL_SPS_POLOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 1143 #define RLY_WL_SPS_POLOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 1144 #define RLY_WL_SPS_POLStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 1145 #define RLY_WL_SPS_POLStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 , Value ) 1147 #define RLY_LOGToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 1148 #define RLY_LOGOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 1149 #define RLY_LOGOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 1150 #define RLY_LOGStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 1151 #define RLY_LOGStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 , Value ) 1153 #define RLY_DMP_FIREToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 1154 #define RLY_DMP_FIREOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 1155 #define RLY_DMP_FIREOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 1156 #define RLY_DMP_FIREStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 1157 #define RLY_DMP_FIREStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 , Value ) 1159 #define RLY_AUXToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 1160 #define RLY_AUXOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 1161 #define RLY_AUXOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 1162 #define RLY_AUXStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 1163 #define RLY_AUXStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 , Value ) 1165 #define RLY_CCLToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 1166 #define RLY_CCLOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 1167 #define RLY_CCLOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 1168 #define RLY_CCLStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 1169 #define RLY_CCLStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 , Value ) 1171 #define RLY_WL_MONToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 1172 #define RLY_WL_MONOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 1173 #define RLY_WL_MONOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 1174 #define RLY_WL_MONStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 1175 #define RLY_WL_MONStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 , Value ) 1177 #define RLY_ARMCFToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 1178 #define RLY_ARMCFOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 1179 #define RLY_ARMCFOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 1180 #define RLY_ARMCFStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 1181 #define RLY_ARMCFStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 , Value ) 1183 #define RLY_ARMToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 1184 #define RLY_ARMOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 1185 #define RLY_ARMOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 1186 #define RLY_ARMStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 1187 #define RLY_ARMStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 , Value ) 1189 #define TPAN1Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 1190 #define TPAN1On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 1191 #define TPAN1Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 1192 #define TPAN1StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 1193 #define TPAN1StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 , Value ) 1195 #define TPAN2Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 1196 #define TPAN2On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 1197 #define TPAN2Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 1198 #define TPAN2StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 1199 #define TPAN2StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 , Value ) 1201 #define FSK_DAC_CSToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 1202 #define FSK_DAC_CSOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 1203 #define FSK_DAC_CSOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 1204 #define FSK_DAC_CSStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 1205 #define FSK_DAC_CSStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 , Value ) 1207 #define RLY_COMMToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 1208 #define RLY_COMMOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 1209 #define RLY_COMMOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 1210 #define RLY_COMMStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 1211 #define RLY_COMMStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 , Value ) 1213 #define FSK_DAC_CLRToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 1214 #define FSK_DAC_CLROn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 1215 #define FSK_DAC_CLROff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 1216 #define FSK_DAC_CLRStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 1217 #define FSK_DAC_CLRStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 , Value ) 1219 #define WL_CPS_SWToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 1220 #define WL_CPS_SWOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 1221 #define WL_CPS_SWOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 1222 #define WL_CPS_SWStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 1223 #define WL_CPS_SWStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 , Value ) 1225 #define HVPS_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_5 ) 1227 #define MAN_SIGStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_0 ) 1229 #define DMP_FIRE_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_8 ) 1231 #define NEG_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_4 ) 1233 #define POS_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_15 ) 1235 #define DRUM1_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_2 ) 1237 #define SAFE_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_1 ) 1239 #define DRUM2_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_0 ) 1241 #define LOG_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_3 ) 1243 #define AUX_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_8 ) 1245 #define ARMCF_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_K , PORTS_BIT_POS_1 ) 1247 #define ARM_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_K , PORTS_BIT_POS_2 ) 1249 #define ARMCF_AUTO_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_13 ) 1251 #define FIRE_SW_OFFStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_8 ) 1253 #define FIRE_SW_ONStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_8 ) 1255 #define WL_SPS_POS_DETStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_12 ) 1257 #define WL_SPS_NEG_DETStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_13 ) 1258 #define MAN_CN_PORT_CHANNEL PORT_CHANNEL_A 1259 #define MAN_CN_PORT_BIT PORTS_BIT_POS_0 1260 #define MAN_CN_PORT_INTERRUPT INT_SOURCE_CHANGE_NOTICE_A 1261 #define HVPS_CN_PORT_CHANNEL PORT_CHANNEL_J 1262 #define HVPS_CN_PORT_BIT PORTS_BIT_POS_11 1263 #define HVPS_CN_PORT_INTERRUPT INT_SOURCE_CHANGE_NOTICE_J 1312 #ifndef _DRV_COMMON_H 1313 #define _DRV_COMMON_H 1415 #define DRV_IO_ISBLOCKING( intent ) ( intent & DRV_IO_INTENT_BLOCKING ) 1425 #define DRV_IO_ISNONBLOCKING( intent ) ( intent & DRV_IO_INTENT_NONBLOCKING ) 1435 #define DRV_IO_ISEXCLUSIVE( intent ) ( intent & DRV_IO_INTENT_EXCLUSIVE ) 1491 #define DRV_HANDLE_INVALID ( ( ( DRV_HANDLE ) - 1 ) ) 1502 #define DRV_CONFIG_NOT_SUPPORTED ( ( ( unsigned short ) - 1 ) ) 1517 #define _PLIB_UNSUPPORTED 1525 #include "system/common/sys_module.h" 1537 #define DRV_IC_INDEX_0 0 1538 #define DRV_IC_INDEX_1 1 1539 #define DRV_IC_INDEX_2 2 1540 #define DRV_IC_INDEX_3 3 1541 #define DRV_IC_INDEX_4 4 1542 #define DRV_IC_INDEX_5 5 1543 #define DRV_IC_INDEX_6 6 1544 #define DRV_IC_INDEX_7 7 1545 #define DRV_IC_INDEX_8 8 1546 #define DRV_IC_INDEX_9 9 1547 #define DRV_IC_INDEX_10 10 1548 #define DRV_IC_INDEX_11 11 1549 #define DRV_IC_INDEX_12 12 1550 #define DRV_IC_INDEX_13 13 1551 #define DRV_IC_INDEX_14 14 1552 #define DRV_IC_INDEX_15 15 1584 const SYS_MODULE_INDEX index ,
1585 const SYS_MODULE_INIT *
const init ) ;
1607 const SYS_MODULE_INDEX drvIndex ,
1652 const SYS_MODULE_INDEX drvIndex ,
1785 #ifndef _DRV_IC_STATIC_H 1786 #define _DRV_IC_STATIC_H 1787 #define DRV_IC_Open( drvIndex , intent ) ( drvIndex ) 1788 #define DRV_IC_Close( handle ) 1827 #include "system/devcon/sys_devcon.h" 1828 #include "system/clk/sys_clk.h" 1829 #include "system/int/sys_int.h" 1830 #include "system/tmr/sys_tmr.h" 1872 #ifndef _DRV_ADC_STATIC_H 1873 #define _DRV_ADC_STATIC_H 1874 #include <stdbool.h> 1875 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 1876 #include "peripheral/adchs/plib_adchs.h" 1877 #include "peripheral/int/plib_int.h" 1917 uint8_t bufIndex ) ;
1921 uint8_t bufIndex ) ;
1971 #ifndef _DRV_TMR_STATIC_H 1972 #define _DRV_TMR_STATIC_H 2021 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 2022 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 2023 #include "peripheral/tmr/plib_tmr.h" 2059 #ifndef _TMR_DEFINITIONS_PIC32M_H 2060 #define _TMR_DEFINITIONS_PIC32M_H 2118 #include "system/int/sys_int.h" 2119 #include "system/clk/sys_clk.h" 2138 #define DRV_TMR_INDEX_0 0 2139 #define DRV_TMR_INDEX_1 1 2140 #define DRV_TMR_INDEX_2 2 2141 #define DRV_TMR_INDEX_3 3 2142 #define DRV_TMR_INDEX_4 4 2143 #define DRV_TMR_INDEX_5 5 2144 #define DRV_TMR_INDEX_6 6 2145 #define DRV_TMR_INDEX_7 7 2146 #define DRV_TMR_INDEX_8 8 2147 #define DRV_TMR_INDEX_9 9 2148 #define DRV_TMR_INDEX_10 10 2149 #define DRV_TMR_INDEX_11 11 2160 #define DRV_TMR_INDEX_COUNT TMR_NUMBER_OF_MODULES 2245 uint32_t dividerMin ;
2247 uint32_t dividerMax ;
2250 uint32_t dividerStep ;
2266 SYS_MODULE_INIT moduleInit ;
2268 TMR_MODULE_ID tmrId ;
2272 TMR_PRESCALE prescale ;
2276 INT_SOURCE interruptSource ;
2284 bool asyncWriteEnable ;
2299 uint32_t alarmCount ) ;
2361 const SYS_MODULE_INDEX drvIndex ,
2362 const SYS_MODULE_INIT *
const init ) ;
2402 SYS_MODULE_OBJ
object ) ;
2449 SYS_MODULE_OBJ
object ) ;
2483 SYS_MODULE_OBJ
object ) ;
2537 const SYS_MODULE_INDEX index ,
2638 uint32_t counterPeriod ) ;
3128 TMR_PRESCALE preScale ) ;
3368 #ifndef _DRV_TMR_DEPRECATED_H 3369 #define _DRV_TMR_DEPRECATED_H 3410 #define DRV_TMR_Tasks_ISR( object ) DRV_TMR_Tasks ( object ) 3474 #define DRV_TMR_CounterValue16BitSet( handle , counterPeriod ) DRV_TMR_CounterValueSet ( handle , counterPeriod ) 3539 #define DRV_TMR_CounterValue32BitSet( handle , counterPeriod ) DRV_TMR_CounterValueSet ( handle , counterPeriod ) 3598 #define DRV_TMR_CounterValue16BitGet( handle ) DRV_TMR_CounterValueGet ( handle ) 3659 #define DRV_TMR_CounterValue32BitGet( handle ) DRV_TMR_CounterValueGet ( handle ) 3718 #define DRV_TMR_Alarm16BitRegister( handle , period , isPeriodic , context , callBack ) DRV_TMR_AlarmRegister ( handle , period , isPeriodic , context , callBack ) 3779 #define DRV_TMR_Alarm32BitRegister( handle , period , isPeriodic , context , callBack ) DRV_TMR_AlarmRegister ( handle , period , isPeriodic , context , callBack ) 3809 #define DRV_TMR_AlarmPeriod16BitSet( handle , value ) DRV_TMR_AlarmPeriodSet ( handle , value ) 3841 #define DRV_TMR_AlarmPeriod32BitSet( handle , period ) DRV_TMR_AlarmPeriodSet ( handle , period ) 3872 #define DRV_TMR_AlarmPeriod16BitGet( handle ) DRV_TMR_AlarmPeriodGet ( handle ) 3904 #define DRV_TMR_AlarmPeriod32BitGet( handle ) DRV_TMR_AlarmPeriodGet ( handle ) 3966 #define DRV_TMR_Alarm16BitDeregister( handle ) DRV_TMR_AlarmDeregister ( handle ) 4031 #define DRV_TMR_Alarm32BitDeregister( handle ) DRV_TMR_AlarmDeregister ( handle ) 4048 #include "peripheral/tmr/plib_tmr.h" 4049 #include "peripheral/int/plib_int.h" 4051 #define DRV_TIMER_DIVIDER_MAX_32BIT 0xffffffff 4053 #define DRV_TIMER_DIVIDER_MIN_32BIT 0x2 4055 #define DRV_TIMER_DIVIDER_MAX_16BIT 0x10000 4057 #define DRV_TIMER_DIVIDER_MIN_16BIT 0x2 4076 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 0)));
4082 static inline SYS_STATUS
4085 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 2)));
4096 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 4)));
4107 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 6)));
4117 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 8)));
4126 TMR_PRESCALE prescale ) ;
4157 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 10)));
4186 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 12)));
4192 static inline SYS_STATUS
4195 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 14)));
4206 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 16)));
4217 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 18)));
4227 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 20)));
4236 TMR_PRESCALE prescale ) ;
4267 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 22)));
4296 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 24)));
4302 static inline SYS_STATUS
4305 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 26)));
4316 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 28)));
4327 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 30)));
4337 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 0)));
4346 TMR_PRESCALE prescale ) ;
4377 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 2)));
4406 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 4)));
4412 static inline SYS_STATUS
4415 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 6)));
4426 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 8)));
4437 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 10)));
4447 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 12)));
4456 TMR_PRESCALE prescale ) ;
4487 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 14)));
4516 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 16)));
4522 static inline SYS_STATUS
4525 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 18)));
4536 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 20)));
4547 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 22)));
4557 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 24)));
4566 TMR_PRESCALE prescale ) ;
4597 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 26)));
4616 #include "peripheral/int/plib_int.h" 4658 #ifndef _DRV_PMP_STATIC_H 4659 #define _DRV_PMP_STATIC_H 4660 #include "peripheral/pmp/plib_pmp.h" 4675 PMP_DATA_WAIT_STATES dataWait ,
4676 PMP_STROBE_WAIT_STATES strobeWait ,
4677 PMP_DATA_HOLD_STATES dataHold ) ;
4732 #ifndef _DRV_USART_STATIC_H 4733 #define _DRV_USART_STATIC_H 4772 #ifndef _DRV_USART_STATIC_LOCAL_H 4773 #define _DRV_USART_STATIC_LOCAL_H 4780 #include <stdbool.h> 4817 #ifndef _DRV_USART_H 4818 #define _DRV_USART_H 4858 #ifndef _DRV_USART_DEFINITIONS_H 4859 #define _DRV_USART_DEFINITIONS_H 4865 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 4866 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 4903 #ifndef _PLIB_USART_H 4904 #define _PLIB_USART_H 4947 #ifndef _USART_PROCESSOR_H 4948 #define _USART_PROCESSOR_H 4957 #include <stdbool.h> 4958 #error "No Processor Family specified" 5002 USART_MODULE_ID index ) ;
5032 USART_MODULE_ID index ) ;
5064 USART_MODULE_ID index ) ;
5098 USART_MODULE_ID index ,
5099 USART_BRG_CLOCK_SOURCE brgClockSource ) ;
5128 USART_BRG_CLOCK_SOURCE
5130 USART_MODULE_ID index ) ;
5184 USART_MODULE_ID index ) ;
5214 USART_MODULE_ID index ) ;
5243 USART_MODULE_ID index ) ;
5275 USART_MODULE_ID index ) ;
5306 USART_MODULE_ID index ) ;
5348 USART_MODULE_ID index ) ;
5381 USART_MODULE_ID index ) ;
5413 USART_MODULE_ID index ) ;
5454 USART_MODULE_ID index ,
5455 uint32_t clockFrequency ,
5456 uint32_t baudRate ) ;
5497 USART_MODULE_ID index ,
5498 uint32_t clockFrequency ,
5499 uint32_t baudRate ) ;
5532 USART_MODULE_ID index ,
5533 int32_t clockFrequency ) ;
5568 USART_MODULE_ID index ,
5603 USART_MODULE_ID index ) ;
5638 USART_MODULE_ID index ,
5673 USART_MODULE_ID index ) ;
5705 USART_MODULE_ID index ) ;
5739 USART_MODULE_ID index ) ;
5772 USART_MODULE_ID index ) ;
5805 USART_MODULE_ID index ) ;
5839 USART_MODULE_ID index ,
5884 USART_MODULE_ID index ) ;
5918 USART_MODULE_ID index ) ;
5954 USART_MODULE_ID index ) ;
5991 USART_MODULE_ID index ,
6031 USART_MODULE_ID index ) ;
6069 USART_MODULE_ID index ) ;
6104 USART_MODULE_ID index ) ;
6138 USART_MODULE_ID index ) ;
6172 USART_MODULE_ID index ) ;
6205 USART_MODULE_ID index ) ;
6237 USART_MODULE_ID index ) ;
6269 USART_MODULE_ID index ) ;
6302 USART_MODULE_ID index ) ;
6336 USART_MODULE_ID index ) ;
6365 USART_MODULE_ID index ) ;
6394 USART_MODULE_ID index ) ;
6426 USART_MODULE_ID index ) ;
6458 USART_MODULE_ID index ) ;
6488 USART_MODULE_ID index ) ;
6518 USART_MODULE_ID index ) ;
6547 USART_MODULE_ID index ) ;
6576 USART_MODULE_ID index ) ;
6610 USART_MODULE_ID index ,
6611 USART_TRANSMIT_INTR_MODE fifolevel ) ;
6643 USART_MODULE_ID index ,
6644 USART_RECEIVE_INTR_MODE interruptMode ) ;
6677 USART_MODULE_ID index ,
6678 USART_LINECONTROL_MODE dataFlowConfig ) ;
6711 USART_MODULE_ID index ,
6712 USART_HANDSHAKE_MODE handshakeConfig ) ;
6745 USART_MODULE_ID index ,
6776 USART_MODULE_ID index ) ;
6805 USART_MODULE_ID index ) ;
6836 USART_MODULE_ID index ) ;
6867 USART_MODULE_ID index ) ;
6897 USART_MODULE_ID index ) ;
6929 USART_MODULE_ID index ,
6930 USART_OPERATION_MODE operationmode ) ;
6960 USART_MODULE_ID index ) ;
6993 USART_MODULE_ID index ) ;
7022 USART_MODULE_ID index ) ;
7052 USART_MODULE_ID index ) ;
7088 USART_MODULE_ID index ) ;
7139 USART_MODULE_ID index ,
7142 bool wakeFromSleep ,
7187 USART_MODULE_ID index ,
7188 USART_RECEIVE_INTR_MODE receiveInterruptMode ,
7189 USART_TRANSMIT_INTR_MODE transmitInterruptMode ,
7190 USART_OPERATION_MODE operationMode ) ;
7236 USART_MODULE_ID index ,
7237 uint32_t systemClock ,
7283 USART_MODULE_ID index ) ;
7304 USART_MODULE_ID index ) ;
7325 USART_MODULE_ID index ) ;
7359 USART_MODULE_ID index ) ;
7386 USART_MODULE_ID index ) ;
7412 USART_MODULE_ID index ) ;
7439 USART_MODULE_ID index ) ;
7465 USART_MODULE_ID index ) ;
7490 USART_MODULE_ID index ) ;
7516 USART_MODULE_ID index ) ;
7541 USART_MODULE_ID index ) ;
7567 USART_MODULE_ID index ) ;
7592 USART_MODULE_ID index ) ;
7618 USART_MODULE_ID index ) ;
7645 USART_MODULE_ID index ) ;
7671 USART_MODULE_ID index ) ;
7697 USART_MODULE_ID index ) ;
7724 USART_MODULE_ID index ) ;
7751 USART_MODULE_ID index ) ;
7778 USART_MODULE_ID index ) ;
7804 USART_MODULE_ID index ) ;
7829 USART_MODULE_ID index ) ;
7855 USART_MODULE_ID index ) ;
7882 USART_MODULE_ID index ) ;
7908 USART_MODULE_ID index ) ;
7934 USART_MODULE_ID index ) ;
7959 USART_MODULE_ID index ) ;
7984 USART_MODULE_ID index ) ;
8009 USART_MODULE_ID index ) ;
8035 USART_MODULE_ID index ) ;
8060 USART_MODULE_ID index ) ;
8086 USART_MODULE_ID index ) ;
8112 USART_MODULE_ID index ) ;
8137 USART_MODULE_ID index ) ;
8163 USART_MODULE_ID index ) ;
8188 USART_MODULE_ID index ) ;
8213 USART_MODULE_ID index ) ;
8240 USART_MODULE_ID index ) ;
8265 USART_MODULE_ID index ) ;
8291 USART_MODULE_ID index ) ;
8356 #include "system/common/sys_common.h" 8357 #include "system/common/sys_module.h" 8369 #include "system/int/sys_int.h" 8441 #ifndef _SYS_DMA_DEFINITIONS_H 8442 #define _SYS_DMA_DEFINITIONS_H 8448 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 8449 #include "system/common/sys_common.h" 8450 #include "system/common/sys_module.h" 8520 #ifndef _PLIB_DMA_PROCESSOR_H 8521 #define _PLIB_DMA_PROCESSOR_H 8522 #error "Can't find header" 8566 DMA_MODULE_ID index ,
8567 DMA_CHANNEL channel ) ;
8601 DMA_MODULE_ID index ,
8602 DMA_CHANNEL channel ,
8603 DMA_CHANNEL_COLLISION collisonType ) ;
8635 DMA_MODULE_ID index ,
8636 DMA_CHANNEL channel ) ;
8668 DMA_MODULE_ID index ,
8669 DMA_CHANNEL channel ) ;
8707 DMA_MODULE_ID index ,
8708 DMA_CHANNEL channel ,
8709 DMA_CHANNEL_PRIORITY channelPriority ) ;
8738 DMA_CHANNEL_PRIORITY
8740 DMA_MODULE_ID index ,
8741 DMA_CHANNEL channel ) ;
8769 DMA_MODULE_ID index ,
8770 DMA_CHANNEL_PRIORITY channelPriority ) ;
8795 DMA_CHANNEL_PRIORITY
8797 DMA_MODULE_ID index ) ;
8827 DMA_MODULE_ID index ,
8828 DMA_CHANNEL channel ) ;
8859 DMA_MODULE_ID index ,
8860 DMA_CHANNEL channel ) ;
8889 DMA_MODULE_ID index ,
8890 DMA_CHANNEL channel ) ;
8919 DMA_MODULE_ID index ,
8920 DMA_CHANNEL channel ) ;
8951 DMA_MODULE_ID index ,
8952 DMA_CHANNEL channel ) ;
8981 DMA_MODULE_ID index ,
8982 DMA_CHANNEL channel ) ;
9013 DMA_MODULE_ID index ,
9014 DMA_CHANNEL channel ) ;
9045 DMA_MODULE_ID index ,
9046 DMA_CHANNEL channel ) ;
9075 DMA_MODULE_ID index ,
9076 DMA_CHANNEL channel ) ;
9107 DMA_MODULE_ID index ,
9108 DMA_CHANNEL channel ) ;
9137 DMA_MODULE_ID index ,
9138 DMA_CHANNEL channel ) ;
9168 DMA_MODULE_ID index ,
9169 DMA_CHANNEL channel ) ;
9199 DMA_MODULE_ID index ,
9200 DMA_CHANNEL channel ) ;
9230 DMA_MODULE_ID index ,
9231 DMA_CHANNEL channel ) ;
9261 DMA_MODULE_ID index ,
9262 DMA_CHANNEL channel ) ;
9293 DMA_MODULE_ID index ,
9294 DMA_CHANNEL channel ) ;
9325 DMA_MODULE_ID index ,
9326 DMA_CHANNEL channel ,
9327 DMA_CHANNEL_TRANSFER_DIRECTION chTransferDirection ) ;
9356 DMA_CHANNEL_TRANSFER_DIRECTION
9358 DMA_MODULE_ID index ,
9359 DMA_CHANNEL channel ) ;
9395 DMA_MODULE_ID index ,
9396 DMA_CHANNEL channel ,
9398 DMA_ADDRESS_OFFSET_TYPE offset ) ;
9431 DMA_MODULE_ID index ,
9432 DMA_CHANNEL channel ,
9433 DMA_ADDRESS_OFFSET_TYPE offset ) ;
9464 DMA_MODULE_ID index ,
9465 DMA_CHANNEL channel ,
9466 uint16_t peripheraladdress ) ;
9494 DMA_MODULE_ID index ,
9495 DMA_CHANNEL channel ) ;
9526 DMA_MODULE_ID index ,
9527 DMA_CHANNEL channel ,
9528 uint16_t transferCount ) ;
9556 DMA_MODULE_ID index ,
9557 DMA_CHANNEL channel ) ;
9590 DMA_MODULE_ID index ,
9591 DMA_CHANNEL channel ,
9592 DMA_SOURCE_ADDRESSING_MODE sourceAddressMode ) ;
9620 DMA_SOURCE_ADDRESSING_MODE
9622 DMA_MODULE_ID index ,
9623 DMA_CHANNEL channel ) ;
9656 DMA_MODULE_ID index ,
9657 DMA_CHANNEL channel ,
9658 DMA_DESTINATION_ADDRESSING_MODE destinationAddressMode ) ;
9687 DMA_DESTINATION_ADDRESSING_MODE
9689 DMA_MODULE_ID index ,
9690 DMA_CHANNEL channel ) ;
9723 DMA_MODULE_ID index ,
9724 DMA_CHANNEL channel ,
9725 DMA_CHANNEL_ADDRESSING_MODE channelAddressMode ) ;
9753 DMA_CHANNEL_ADDRESSING_MODE
9755 DMA_MODULE_ID index ,
9756 DMA_CHANNEL channel ) ;
9794 DMA_MODULE_ID index ,
9795 DMA_CHANNEL channel ,
9796 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9832 DMA_MODULE_ID index ,
9833 DMA_CHANNEL channel ,
9834 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9869 DMA_MODULE_ID index ,
9870 DMA_CHANNEL channel ,
9871 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9900 DMA_CHANNEL_INT_SOURCE
9902 DMA_MODULE_ID index ,
9903 DMA_CHANNEL channel ) ;
9938 DMA_MODULE_ID index ,
9939 DMA_CHANNEL channel ,
9940 DMA_TRIGGER_SOURCE IRQnum ) ;
9975 DMA_MODULE_ID index ,
9976 DMA_CHANNEL channel ,
9977 DMA_TRIGGER_SOURCE IRQ ) ;
10008 DMA_MODULE_ID index ,
10009 DMA_CHANNEL channel ,
10010 DMA_CHANNEL_DATA_SIZE channelDataSize ) ;
10037 DMA_CHANNEL_DATA_SIZE
10039 DMA_MODULE_ID index ,
10040 DMA_CHANNEL channel ) ;
10074 DMA_MODULE_ID index ,
10075 DMA_CHANNEL channel ,
10076 DMA_TRANSFER_MODE channeltransferMode ) ;
10108 DMA_MODULE_ID index ,
10109 DMA_CHANNEL channel ) ;
10138 DMA_MODULE_ID index ,
10139 DMA_CHANNEL channel ) ;
10169 DMA_MODULE_ID index ,
10170 DMA_CHANNEL channel ) ;
10199 DMA_MODULE_ID index ,
10200 DMA_CHANNEL channel ) ;
10228 DMA_MODULE_ID index ,
10229 DMA_CHANNEL channel ) ;
10259 DMA_MODULE_ID index ,
10260 DMA_CHANNEL channel ) ;
10287 DMA_MODULE_ID index ,
10288 DMA_CHANNEL channel ) ;
10324 DMA_MODULE_ID index ,
10325 DMA_CHANNEL channel ) ;
10356 DMA_MODULE_ID index ,
10357 DMA_CHANNEL channel ) ;
10390 DMA_MODULE_ID index ) ;
10419 DMA_MODULE_ID index ) ;
10449 DMA_MODULE_ID index ) ;
10478 DMA_MODULE_ID index ) ;
10507 DMA_MODULE_ID index ) ;
10537 DMA_MODULE_ID index ) ;
10565 DMA_MODULE_ID index ) ;
10593 DMA_MODULE_ID index ) ;
10621 DMA_MODULE_ID index ) ;
10650 DMA_MODULE_ID index ) ;
10678 DMA_MODULE_ID index ) ;
10712 DMA_MODULE_ID index ) ;
10742 DMA_MODULE_ID index ) ;
10772 DMA_MODULE_ID index ) ;
10801 DMA_MODULE_ID index ) ;
10836 DMA_MODULE_ID index ,
10837 DMA_CHANNEL channel ) ;
10866 DMA_MODULE_ID index ) ;
10898 DMA_MODULE_ID index ,
10899 DMA_CRC_TYPE CRCType ) ;
10930 DMA_MODULE_ID index ) ;
10960 DMA_MODULE_ID index ) ;
10990 DMA_MODULE_ID index ) ;
11020 DMA_MODULE_ID index ) ;
11049 DMA_MODULE_ID index ) ;
11079 DMA_MODULE_ID index ) ;
11108 DMA_MODULE_ID index ) ;
11138 DMA_MODULE_ID index ,
11139 uint8_t polyLength ) ;
11168 DMA_MODULE_ID index ) ;
11197 DMA_MODULE_ID index ,
11198 DMA_CRC_BIT_ORDER bitOrder ) ;
11229 DMA_MODULE_ID index ) ;
11258 DMA_MODULE_ID index ) ;
11288 DMA_MODULE_ID index ,
11289 DMA_CRC_BYTE_ORDER byteOrder ) ;
11318 DMA_MODULE_ID index ) ;
11349 DMA_MODULE_ID index ) ;
11381 DMA_MODULE_ID index ,
11382 uint32_t DMACRCdata ) ;
11413 DMA_MODULE_ID index ) ;
11446 DMA_MODULE_ID index ,
11447 uint32_t DMACRCXOREnableMask ) ;
11485 DMA_MODULE_ID index ,
11486 DMA_CHANNEL dmaChannel ) ;
11523 DMA_MODULE_ID index ,
11524 DMA_CHANNEL dmaChannel ,
11525 uint32_t sourceStartAddress ) ;
11559 DMA_MODULE_ID index ,
11560 DMA_CHANNEL dmaChannel ) ;
11598 DMA_MODULE_ID index ,
11599 DMA_CHANNEL dmaChannel ,
11600 uint32_t destinationStartAddress ) ;
11640 DMA_MODULE_ID index ,
11641 DMA_CHANNEL dmaChannel ) ;
11680 DMA_MODULE_ID index ,
11681 DMA_CHANNEL dmaChannel ,
11682 uint16_t sourceSize ) ;
11717 DMA_MODULE_ID index ,
11718 DMA_CHANNEL dmaChannel ) ;
11755 DMA_MODULE_ID index ,
11756 DMA_CHANNEL dmaChannel ,
11757 uint16_t destinationSize ) ;
11791 DMA_MODULE_ID index ,
11792 DMA_CHANNEL dmaChannel ) ;
11827 DMA_MODULE_ID index ,
11828 DMA_CHANNEL dmaChannel ) ;
11863 DMA_MODULE_ID index ,
11864 DMA_CHANNEL dmaChannel ) ;
11901 DMA_MODULE_ID index ,
11902 DMA_CHANNEL dmaChannel ,
11903 uint16_t CellSize ) ;
11937 DMA_MODULE_ID index ,
11938 DMA_CHANNEL dmaChannel ) ;
11975 DMA_MODULE_ID index ,
11976 DMA_CHANNEL dmaChannel ) ;
12015 DMA_MODULE_ID index ,
12016 DMA_CHANNEL dmaChannel ,
12017 uint16_t patternData ) ;
12061 DMA_MODULE_ID index ,
12062 DMA_CHANNEL dmaChannel ,
12063 DMA_INT_TYPE dmaINTSource ) ;
12098 DMA_MODULE_ID index ,
12099 DMA_CHANNEL dmaChannel ,
12100 DMA_INT_TYPE dmaINTSource ) ;
12136 DMA_MODULE_ID index ,
12137 DMA_CHANNEL dmaChannel ,
12138 DMA_INT_TYPE dmaINTSource ) ;
12172 DMA_MODULE_ID index ,
12173 DMA_CHANNEL dmaChannel ,
12174 DMA_INT_TYPE dmaINTSource ) ;
12208 DMA_MODULE_ID index ,
12209 DMA_CHANNEL dmaChannel ,
12210 DMA_INT_TYPE dmaINTSource ) ;
12248 DMA_MODULE_ID index ,
12249 DMA_CHANNEL dmaChannel ,
12250 DMA_INT_TYPE dmaINTSource ) ;
12283 DMA_MODULE_ID index ,
12284 DMA_CHANNEL dmaChannel ,
12285 DMA_PATTERN_LENGTH patternLen ) ;
12318 DMA_MODULE_ID index ,
12319 DMA_CHANNEL dmaChannel ) ;
12349 DMA_MODULE_ID index ,
12350 DMA_CHANNEL channel ) ;
12383 DMA_MODULE_ID index ,
12384 DMA_CHANNEL channel ) ;
12414 DMA_MODULE_ID index ,
12415 DMA_CHANNEL channel ) ;
12447 DMA_MODULE_ID index ,
12448 DMA_CHANNEL channel ,
12449 uint8_t pattern ) ;
12480 DMA_MODULE_ID index ,
12481 DMA_CHANNEL channel ) ;
12513 DMA_MODULE_ID index ) ;
12538 DMA_MODULE_ID index ) ;
12562 DMA_MODULE_ID index ) ;
12587 DMA_MODULE_ID index ) ;
12610 DMA_MODULE_ID index ) ;
12634 DMA_MODULE_ID index ) ;
12657 DMA_MODULE_ID index ) ;
12681 DMA_MODULE_ID index ) ;
12705 DMA_MODULE_ID index ) ;
12730 DMA_MODULE_ID index ) ;
12754 DMA_MODULE_ID index ) ;
12778 DMA_MODULE_ID index ) ;
12801 DMA_MODULE_ID index ) ;
12825 DMA_MODULE_ID index ) ;
12849 DMA_MODULE_ID index ) ;
12873 DMA_MODULE_ID index ) ;
12897 DMA_MODULE_ID index ) ;
12921 DMA_MODULE_ID index ) ;
12944 DMA_MODULE_ID index ) ;
12969 DMA_MODULE_ID index ) ;
12994 DMA_MODULE_ID index ) ;
13018 DMA_MODULE_ID index ) ;
13043 DMA_MODULE_ID index ) ;
13067 DMA_MODULE_ID index ) ;
13091 DMA_MODULE_ID index ) ;
13117 DMA_MODULE_ID index ) ;
13142 DMA_MODULE_ID index ) ;
13166 DMA_MODULE_ID index ) ;
13191 DMA_MODULE_ID index ) ;
13214 DMA_MODULE_ID index ) ;
13237 DMA_MODULE_ID index ) ;
13260 DMA_MODULE_ID index ) ;
13283 DMA_MODULE_ID index ) ;
13308 DMA_MODULE_ID index ) ;
13333 DMA_MODULE_ID index ) ;
13357 DMA_MODULE_ID index ) ;
13382 DMA_MODULE_ID index ) ;
13406 DMA_MODULE_ID index ) ;
13430 DMA_MODULE_ID index ) ;
13453 DMA_MODULE_ID index ) ;
13476 DMA_MODULE_ID index ) ;
13500 DMA_MODULE_ID index ) ;
13524 DMA_MODULE_ID index ) ;
13548 DMA_MODULE_ID index ) ;
13575 #define DMA_CHANNEL_NONE ( ( DMA_CHANNEL ) - 1 ) 13588 #define DMA_CHANNEL_ANY ( ( DMA_CHANNEL ) - 2 ) 13601 #define SYS_DMA_CHANNEL_COUNT DMA_NUMBER_OF_CHANNELS 13631 #define SYS_DMA_CHANNEL_HANDLE_INVALID ( ( SYS_DMA_CHANNEL_HANDLE ) ( - 1 ) ) 13805 DMA_CRC_TYPE type ;
13811 uint8_t polyLength ;
13814 DMA_CRC_BIT_ORDER bitOrder ;
13817 DMA_CRC_BYTE_ORDER byteOrder ;
13827 uint32_t xorBitMask ;
13952 SYS_MODULE_OBJ
object ,
13953 DMA_CHANNEL activeChannel ) ;
13956 #define SYS_DMA_TasksISR( object , activeChannel ) SYS_DMA_Tasks ( object , activeChannel ) 14001 uintptr_t contextHandle ) ;
14047 const SYS_MODULE_INIT *
const init ) ;
14098 DMA_CHANNEL channel ) ;
14184 DMA_TRIGGER_SOURCE eventSrc ) ;
14262 DMA_PATTERN_LENGTH length ,
14264 uint8_t ignorePattern ) ;
14517 const void * srcAddr ,
14519 const void * destAddr ,
14521 size_t cellSize ) ;
14618 const void * srcAddr ,
14620 const void * destAddr ,
14622 size_t cellSize ) ;
14818 const uintptr_t contextHandle ) ;
15114 DMA_TRIGGER_SOURCE eventSrc ) ;
15293 SYS_MODULE_OBJ
object ,
15294 DMA_CHANNEL activeChannel ) ;
15304 SYS_MODULE_OBJ
object ) ;
15314 SYS_MODULE_OBJ
object ,
15315 DMA_CHANNEL activeChannel ) ;
15342 #define DRV_USART_INDEX_0 0 15343 #define DRV_USART_INDEX_1 1 15344 #define DRV_USART_INDEX_2 2 15345 #define DRV_USART_INDEX_3 3 15346 #define DRV_USART_INDEX_4 4 15347 #define DRV_USART_INDEX_5 5 15361 #define DRV_USART_COUNT USART_NUMBER_OF_MODULES 15372 #define DRV_USART_WRITE_ERROR ( ( uint32_t ) ( - 1 ) ) 15383 #define DRV_USART_READ_ERROR ( ( uint32_t ) ( - 1 ) ) 15417 #define DRV_USART_BUFFER_HANDLE_INVALID ( ( DRV_USART_BUFFER_HANDLE ) ( - 1 ) ) 15568 uintptr_t context ) ;
15616 USART_HANDSHAKE_MODE_FLOW_CONTROL
15620 USART_HANDSHAKE_MODE_SIMPLEX
15782 } AddressedModeInit ;
15807 = USART_ERROR_PARITY
15812 = USART_ERROR_FRAMING
15817 = USART_ERROR_RECEIVER_OVERRUN
15899 SYS_MODULE_INIT moduleInit ;
15903 USART_MODULE_ID usartID ;
15921 uint32_t brgClock ;
15937 USART_OPERATION_MODE linesEnable ;
15941 INT_SOURCE interruptTransmit ;
15945 INT_SOURCE interruptReceive ;
15949 INT_SOURCE interruptError ;
15954 unsigned int queueSizeReceive ;
15959 unsigned int queueSizeTransmit ;
15963 DMA_CHANNEL dmaChannelTransmit ;
15967 DMA_CHANNEL dmaChannelReceive ;
15971 INT_SOURCE dmaInterruptTransmit ;
15975 INT_SOURCE dmaInterruptReceive ;
16059 const SYS_MODULE_INDEX index ,
16060 const SYS_MODULE_INIT *
const init ) ;
16098 SYS_MODULE_OBJ
object ) ;
16136 SYS_MODULE_OBJ
object ) ;
16177 SYS_MODULE_OBJ
object ) ;
16218 SYS_MODULE_OBJ
object ) ;
16259 SYS_MODULE_OBJ
object ) ;
16338 const SYS_MODULE_INDEX index ,
16522 const size_t size ) ;
16715 const size_t size ) ;
16803 const uintptr_t context ) ;
17070 const size_t numbytes ) ;
17138 const size_t numbytes ) ;
17275 const uint8_t byte ) ;
17493 const SYS_MODULE_INDEX index ,
17546 const SYS_MODULE_INDEX index ,
17595 const SYS_MODULE_INDEX index ,
17810 #ifndef _DRV_USART_FEATURE_MAPPING_H 17811 #define _DRV_USART_FEATURE_MAPPING_H 17820 #define _DRV_USART_InterruptSourceIsEnabled( source ) false 17821 #define _DRV_USART_InterruptSourceEnable( source ) 17822 #define _DRV_USART_InterruptSourceDisable( source ) false 17823 #define _DRV_USART_InterruptSourceStatusClear( source ) SYS_INT_SourceStatusClear ( source ) 17824 #define _DRV_USART_SEM_POST( x ) OSAL_SEM_Post ( x ) 17825 #define _DRV_USART_TAKE_MUTEX( x , y ) OSAL_MUTEX_Lock ( x , y ) 17826 #define _DRV_USART_RELEASE_MUTEX( x ) OSAL_MUTEX_Unlock ( x ) 17827 #define _SYS_DMA_ChannelForceStart( channelHandle ) SYS_DMA_ChannelForceStart ( channelHandle ) 17830 #define _DRV_USART_ALWAYS_NON_BLOCKING ( DRV_IO_INTENT_NONBLOCKING ) 17839 #define _DRV_USART_TRANSMIT_BUFFER_QUEUE_TASKS( x ) _DRV_USART_ByteTransmitTasks ( x ) 17840 #define _DRV_USART_RECEIVE_BUFFER_QUEUE_TASKS( x ) _DRV_USART_ByteReceiveTasks ( x ) 17841 #define _DRV_USART_ERROR_TASKS( x ) _DRV_USART_ByteErrorTasks ( x ) 17842 #define _DRV_USART_CLIENT_BUFFER_QUEUE_OBJECTS_REMOVE( x ) true 17843 #define _DRV_USART_ByteModelInterruptSourceEnable( source ) 17856 #include "system/clk/sys_clk.h" 17857 #include "system/int/sys_int.h" 17895 #ifndef _SYS_DEBUG_H 17896 #define _SYS_DEBUG_H 17897 #include "C:\microchip\harmony\v2_06\framework\system\system.h" 17900 #define SYS_DEBUG_BUFFER_DMA_READY 17950 #define SYS_DEBUG_INDEX_0 0 17966 SYS_MODULE_INIT moduleInit ;
17970 SYS_MODULE_INDEX consoleIndex ;
18018 const SYS_MODULE_INDEX index ,
18019 const SYS_MODULE_INIT *
const init ) ;
18059 SYS_MODULE_OBJ
object ,
18060 const SYS_MODULE_INIT *
const init ) ;
18090 SYS_MODULE_OBJ
object ) ;
18123 SYS_MODULE_OBJ
object ) ;
18167 SYS_MODULE_OBJ
object ) ;
18210 const char * message ) ;
18260 const char * format ,
18350 #define _SYS_DEBUG_MESSAGE( level , message ) do { if ( ( level ) <= SYS_DEBUG_ErrorLevelGet ( ) ) SYS_DEBUG_Message ( message ) ; } while ( 0 ) 18394 #define _SYS_DEBUG_PRINT( level , format ,... ) do { if ( ( level ) <= SYS_DEBUG_ErrorLevelGet ( ) ) SYS_DEBUG_Print ( format , ## __VA_ARGS__ ) ; } while ( 0 ) 18437 #define SYS_MESSAGE( message ) 18470 #define SYS_DEBUG_MESSAGE( level , message ) 18517 #define SYS_PRINT( fmt ,... ) 18565 #define SYS_DEBUG_PRINT( level , fmt ,... ) 18590 #define SYS_DEBUG_BreakPoint( ) 18599 #define SYS_DEBUG( level , message ) SYS_DEBUG_MESSAGE ( level , message ) 18600 #define SYS_ERROR( level , fmt ,... ) SYS_DEBUG_PRINT ( level , fmt , ## __VA_ARGS__ ) 18601 #define SYS_ERROR_PRINT( level , fmt ,... ) SYS_DEBUG_PRINT ( level , fmt , ## __VA_ARGS__ ) 18618 #define _DRV_USART_RX_DEPTH 9 18684 const SYS_MODULE_INDEX index ,
18709 const uint8_t byte ) ;
18780 #ifndef _SYS_PORTS_H 18781 #define _SYS_PORTS_H 18820 #ifndef _SYS_PORTS_DEFINITIONS_H 18821 #define _SYS_PORTS_DEFINITIONS_H 18827 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 18828 #include "system/common/sys_common.h" 18829 #include "system/common/sys_module.h" 18866 #ifndef _PLIB_PORTS_H 18867 #define _PLIB_PORTS_H 18868 #include <stdint.h> 18869 #include <stddef.h> 18934 #ifndef _PLIB_PORTS_PROCESSOR_H 18935 #define _PLIB_PORTS_PROCESSOR_H 18936 #error "Can't find header" 18986 PORTS_MODULE_ID index ,
18987 PORTS_REMAP_INPUT_FUNCTION inputFunction ,
18988 PORTS_REMAP_INPUT_PIN remapInputPin ) ;
19031 PORTS_MODULE_ID index ,
19032 PORTS_REMAP_OUTPUT_FUNCTION outputFunction ,
19033 PORTS_REMAP_OUTPUT_PIN remapOutputPin ) ;
19068 PORTS_MODULE_ID index ,
19069 PORTS_ANALOG_PIN pin ,
19070 PORTS_PIN_MODE mode ) ;
19110 PORTS_MODULE_ID index ,
19111 PORTS_CHANNEL channel ,
19112 PORTS_BIT_POS bitPos ,
19113 PORTS_PIN_MODE mode ) ;
19148 PORTS_MODULE_ID index ,
19149 PORTS_CHANNEL channel ,
19150 PORTS_BIT_POS bitPos ) ;
19184 PORTS_MODULE_ID index ,
19185 PORTS_CHANNEL channel ,
19186 PORTS_BIT_POS bitPos ) ;
19223 PORTS_MODULE_ID index ,
19224 PORTS_CHANNEL channel ,
19225 PORTS_BIT_POS bitPos ) ;
19266 PORTS_MODULE_ID index ,
19267 PORTS_CHANNEL channel ,
19268 PORTS_BIT_POS bitPos ) ;
19307 PORTS_MODULE_ID index ,
19308 PORTS_CHANNEL channel ,
19309 PORTS_BIT_POS bitPos ) ;
19347 PORTS_MODULE_ID index ,
19348 PORTS_CHANNEL channel ,
19349 PORTS_BIT_POS bitPos ) ;
19384 PORTS_MODULE_ID index ,
19385 PORTS_CHANNEL channel ) ;
19420 PORTS_MODULE_ID index ,
19421 PORTS_CHANNEL channel ) ;
19458 PORTS_MODULE_ID index ,
19459 PORTS_CHANNEL channel ) ;
19496 PORTS_MODULE_ID index ,
19497 PORTS_CHANNEL channel ) ;
19534 PORTS_MODULE_ID index ,
19535 PORTS_CHANNEL channel ,
19536 PORTS_BIT_POS bitPos ) ;
19573 PORTS_MODULE_ID index ,
19574 PORTS_CHANNEL channel ,
19575 PORTS_BIT_POS bitPos ) ;
19613 PORTS_MODULE_ID index ,
19614 PORTS_CHANNEL channel ,
19615 PORTS_BIT_POS bitPos ) ;
19652 PORTS_MODULE_ID index ,
19653 PORTS_CHANNEL channel ,
19654 PORTS_BIT_POS bitPos ,
19689 PORTS_MODULE_ID index ,
19690 PORTS_CHANNEL channel ,
19691 PORTS_BIT_POS bitPos ) ;
19725 PORTS_MODULE_ID index ,
19726 PORTS_CHANNEL channel ,
19727 PORTS_BIT_POS bitPos ) ;
19761 PORTS_MODULE_ID index ,
19762 PORTS_CHANNEL channel ,
19763 PORTS_BIT_POS bitPos ) ;
19798 PORTS_MODULE_ID index ,
19799 PORTS_CHANNEL channel ,
19800 PORTS_BIT_POS bitPos ) ;
19835 PORTS_MODULE_ID index ,
19836 PORTS_CHANNEL channel ,
19837 PORTS_BIT_POS bitPos ) ;
19871 PORTS_MODULE_ID index ,
19872 PORTS_CHANNEL channel ,
19873 PORTS_BIT_POS bitPos ) ;
19907 PORTS_MODULE_ID index ,
19908 PORTS_CHANNEL channel ,
19909 PORTS_BIT_POS bitPos ) ;
19947 PORTS_MODULE_ID index ,
19948 PORTS_CHANNEL channel ) ;
19982 PORTS_MODULE_ID index ,
19983 PORTS_CHANNEL channel ) ;
20017 PORTS_MODULE_ID index ,
20018 PORTS_CHANNEL channel ,
20061 PORTS_MODULE_ID index ,
20062 PORTS_CHANNEL channel ,
20098 PORTS_MODULE_ID index ,
20099 PORTS_CHANNEL channel ,
20134 PORTS_MODULE_ID index ,
20135 PORTS_CHANNEL channel ,
20171 PORTS_MODULE_ID index ,
20172 PORTS_CHANNEL channel ,
20207 PORTS_MODULE_ID index ,
20208 PORTS_CHANNEL channel ,
20241 PORTS_MODULE_ID index ,
20242 PORTS_CHANNEL channel ) ;
20276 PORTS_MODULE_ID index ,
20277 PORTS_CHANNEL channel ,
20313 PORTS_MODULE_ID index ,
20314 PORTS_CHANNEL channel ,
20360 PORTS_MODULE_ID index ,
20361 PORTS_CHANNEL channel ,
20363 PORTS_PIN_MODE mode ) ;
20405 PORTS_MODULE_ID index ,
20406 PORTS_CHANNEL channel ,
20449 PORTS_MODULE_ID index ,
20450 PORTS_CHANNEL channel ,
20490 PORTS_MODULE_ID index ,
20491 PORTS_CHANNEL channel ,
20531 PORTS_MODULE_ID index ,
20532 PORTS_CHANNEL channel ,
20576 PORTS_MODULE_ID index ,
20577 PORTS_CHANNEL channel ,
20621 PORTS_MODULE_ID index ,
20622 PORTS_CHANNEL channel ,
20668 PORTS_MODULE_ID index ,
20669 PORTS_AN_PIN anPins ,
20670 PORTS_PIN_MODE mode ) ;
20713 PORTS_MODULE_ID index ,
20714 PORTS_CN_PIN cnPins ) ;
20758 PORTS_MODULE_ID index ,
20759 PORTS_CN_PIN cnPins ) ;
20802 PORTS_MODULE_ID index ,
20803 PORTS_CN_PIN cnPins ) ;
20846 PORTS_MODULE_ID index ,
20847 PORTS_CN_PIN cnPins ) ;
20881 PORTS_MODULE_ID index ) ;
20914 PORTS_MODULE_ID index ) ;
20950 PORTS_MODULE_ID index ,
20951 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20987 PORTS_MODULE_ID index ,
20988 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
21025 PORTS_MODULE_ID index ) ;
21059 PORTS_MODULE_ID index ) ;
21095 PORTS_MODULE_ID index ,
21096 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
21132 PORTS_MODULE_ID index ,
21133 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
21178 PORTS_MODULE_ID index ,
21179 PORTS_CHANNEL channel ,
21181 PORTS_PIN_SLEW_RATE slewRate ) ;
21218 PORTS_PIN_SLEW_RATE
21220 PORTS_MODULE_ID index ,
21221 PORTS_CHANNEL channel ,
21222 PORTS_BIT_POS bitPos ) ;
21261 PORTS_MODULE_ID index ,
21262 PORTS_CHANNEL channel ,
21263 PORTS_CHANGE_NOTICE_METHOD changeNoticeMethod ) ;
21296 PORTS_CHANGE_NOTICE_METHOD
21298 PORTS_MODULE_ID index ,
21299 PORTS_CHANNEL channel ) ;
21347 PORTS_MODULE_ID index ,
21348 PORTS_CHANNEL channel ,
21398 PORTS_MODULE_ID index ,
21399 PORTS_CHANNEL channel ,
21447 PORTS_MODULE_ID index ,
21448 PORTS_CHANNEL channel ,
21449 PORTS_BIT_POS bitPos ,
21450 PORTS_CHANGE_NOTICE_EDGE cnEdgeType ) ;
21493 PORTS_MODULE_ID index ,
21494 PORTS_CHANNEL channel ,
21495 PORTS_BIT_POS bitPos ) ;
21526 PORTS_MODULE_ID index ) ;
21550 PORTS_MODULE_ID index ) ;
21574 PORTS_MODULE_ID index ) ;
21598 PORTS_MODULE_ID index ) ;
21623 PORTS_MODULE_ID index ) ;
21648 PORTS_MODULE_ID index ) ;
21679 PORTS_MODULE_ID index ) ;
21707 PORTS_MODULE_ID index ) ;
21734 PORTS_MODULE_ID index ) ;
21759 PORTS_MODULE_ID index ) ;
21786 PORTS_MODULE_ID index ) ;
21811 PORTS_MODULE_ID index ) ;
21838 PORTS_MODULE_ID index ) ;
21863 PORTS_MODULE_ID index ) ;
21891 PORTS_MODULE_ID index ) ;
21919 PORTS_MODULE_ID index ) ;
21947 PORTS_MODULE_ID index ) ;
21973 PORTS_MODULE_ID index ) ;
21999 PORTS_MODULE_ID index ) ;
22025 PORTS_MODULE_ID index ) ;
22050 PORTS_MODULE_ID index ) ;
22076 PORTS_MODULE_ID index ) ;
22103 PORTS_MODULE_ID index ) ;
22128 PORTS_MODULE_ID index ) ;
22163 #ifndef _PLIB_PORTS_COMPATIBILITY_H 22164 #define _PLIB_PORTS_COMPATIBILITY_H 22165 #include <stdint.h> 22166 #include <stddef.h> 22201 #define PLIB_PORTS_ChangeNoticePerPortHasOccured PLIB_PORTS_ChangeNoticePerPortHasOccurred 22218 #include "system/int/sys_int.h" 22352 PORTS_MODULE_ID index ,
22353 PORTS_CHANNEL channel ) ;
22385 PORTS_MODULE_ID index ,
22386 PORTS_CHANNEL channel ,
22416 PORTS_MODULE_ID index ,
22417 PORTS_CHANNEL channel ) ;
22455 PORTS_MODULE_ID index ,
22456 PORTS_CHANNEL channel ,
22490 PORTS_MODULE_ID index ,
22491 PORTS_CHANNEL channel ,
22528 PORTS_MODULE_ID index ,
22530 PORTS_CHANNEL channel ,
22560 PORTS_MODULE_ID index ,
22561 PORTS_CHANNEL channel ) ;
22592 PORTS_MODULE_ID index ,
22593 PORTS_CHANNEL channel ,
22625 PORTS_MODULE_ID index ,
22626 PORTS_CHANNEL channel ,
22658 PORTS_MODULE_ID index ,
22659 PORTS_CHANNEL channel ,
22693 PORTS_MODULE_ID index ,
22694 PORTS_CHANNEL channel ) ;
22734 PORTS_MODULE_ID index ,
22735 PORTS_REMAP_INPUT_FUNCTION
function ,
22736 PORTS_REMAP_INPUT_PIN remapPin ) ;
22771 PORTS_MODULE_ID index ,
22772 PORTS_REMAP_OUTPUT_FUNCTION
function ,
22773 PORTS_REMAP_OUTPUT_PIN remapPin ) ;
22806 PORTS_MODULE_ID index ) ;
22834 PORTS_MODULE_ID index ) ;
22868 PORTS_MODULE_ID index ,
22869 PORTS_CHANGE_NOTICE_PIN pinNum ,
22901 PORTS_MODULE_ID index ,
22902 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
22931 PORTS_MODULE_ID index ) ;
22960 PORTS_MODULE_ID index ) ;
22991 PORTS_MODULE_ID index ,
22992 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
23023 PORTS_MODULE_ID index ,
23024 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
23063 PORTS_MODULE_ID index ,
23064 PORTS_ANALOG_PIN pin ,
23065 PORTS_PIN_MODE mode ) ;
23102 PORTS_MODULE_ID index ,
23103 PORTS_CHANNEL channel ,
23104 PORTS_BIT_POS bitPos ,
23139 PORTS_MODULE_ID index ,
23140 PORTS_CHANNEL channel ,
23141 PORTS_BIT_POS bitPos ) ;
23174 PORTS_MODULE_ID index ,
23175 PORTS_CHANNEL channel ,
23176 PORTS_BIT_POS bitPos ) ;
23209 PORTS_MODULE_ID index ,
23210 PORTS_CHANNEL channel ,
23211 PORTS_BIT_POS bitPos ) ;
23244 PORTS_MODULE_ID index ,
23245 PORTS_CHANNEL channel ,
23246 PORTS_BIT_POS bitPos ) ;
23279 PORTS_MODULE_ID index ,
23280 PORTS_CHANNEL channel ,
23281 PORTS_BIT_POS bitPos ) ;
23318 PORTS_MODULE_ID index ,
23320 PORTS_CHANNEL channel ,
23321 PORTS_BIT_POS bitPos ) ;
23354 PORTS_MODULE_ID index ,
23355 PORTS_CHANNEL channel ,
23356 PORTS_BIT_POS bitPos ) ;
23389 PORTS_MODULE_ID index ,
23390 PORTS_CHANNEL channel ,
23391 PORTS_BIT_POS bitPos ) ;
23424 PORTS_MODULE_ID index ,
23425 PORTS_CHANNEL channel ,
23426 PORTS_BIT_POS bitPos ) ;
23459 PORTS_MODULE_ID index ,
23460 PORTS_CHANNEL channel ,
23461 PORTS_BIT_POS bitPos ) ;
23494 PORTS_MODULE_ID index ,
23495 PORTS_CHANNEL channel ,
23496 PORTS_BIT_POS bitPos ) ;
23529 PORTS_MODULE_ID index ,
23530 PORTS_CHANNEL channel ,
23531 PORTS_BIT_POS bitPos ) ;
23564 PORTS_MODULE_ID index ,
23565 PORTS_CHANNEL channel ,
23566 PORTS_BIT_POS bitPos ,
23649 #ifndef _DRV_SPI_DEFINITIONS_H 23650 #define _DRV_SPI_DEFINITIONS_H 23656 #include <stdint.h> 23657 #include <stdbool.h> 23658 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 23659 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 23695 #ifndef _PLIB_SPI_H 23696 #define _PLIB_SPI_H 23730 #ifndef _PLIB_SPI_PROCESSOR_H 23731 #define _PLIB_SPI_PROCESSOR_H 23732 #error "Can't find header" 23777 SPI_MODULE_ID index ) ;
23807 SPI_MODULE_ID index ) ;
23839 SPI_MODULE_ID index ) ;
23871 SPI_MODULE_ID index ) ;
23905 SPI_MODULE_ID index ) ;
23935 SPI_MODULE_ID index ) ;
23972 SPI_MODULE_ID index ) ;
24011 SPI_MODULE_ID index ) ;
24041 SPI_MODULE_ID index ,
24072 SPI_MODULE_ID index ,
24106 SPI_MODULE_ID index ,
24107 SPI_COMMUNICATION_WIDTH width ) ;
24142 SPI_MODULE_ID index ,
24143 SPI_AUDIO_COMMUNICATION_WIDTH mode ) ;
24175 SPI_MODULE_ID index ,
24176 SPI_INPUT_SAMPLING_PHASE phase ) ;
24208 SPI_MODULE_ID index ,
24209 SPI_OUTPUT_DATA_PHASE phase ) ;
24240 SPI_MODULE_ID index ,
24241 SPI_CLOCK_POLARITY polarity ) ;
24271 SPI_MODULE_ID index ) ;
24301 SPI_MODULE_ID index ) ;
24339 SPI_MODULE_ID index ,
24340 uint32_t clockFrequency ,
24341 uint32_t baudRate ) ;
24372 SPI_MODULE_ID index ) ;
24404 SPI_MODULE_ID index ) ;
24437 SPI_MODULE_ID index ) ;
24470 SPI_MODULE_ID index ) ;
24502 SPI_MODULE_ID index ) ;
24532 SPI_MODULE_ID index ) ;
24563 SPI_MODULE_ID index ) ;
24594 SPI_MODULE_ID index ) ;
24625 SPI_MODULE_ID index ) ;
24657 SPI_MODULE_ID index ,
24658 SPI_FIFO_TYPE type ) ;
24690 SPI_MODULE_ID index ) ;
24722 SPI_MODULE_ID index ) ;
24756 SPI_MODULE_ID index ,
24757 SPI_FIFO_INTERRUPT mode ) ;
24787 SPI_MODULE_ID index ) ;
24817 SPI_MODULE_ID index ) ;
24849 SPI_MODULE_ID index ,
24850 SPI_FRAME_PULSE_DIRECTION direction ) ;
24883 SPI_MODULE_ID index ,
24884 SPI_FRAME_PULSE_POLARITY polarity ) ;
24917 SPI_MODULE_ID index ,
24918 SPI_FRAME_PULSE_EDGE edge ) ;
24951 SPI_MODULE_ID index ,
24952 SPI_FRAME_PULSE_WIDTH width ) ;
24986 SPI_MODULE_ID index ,
24987 SPI_FRAME_SYNC_PULSE pulse ) ;
25019 SPI_MODULE_ID index ) ;
25049 SPI_MODULE_ID index ) ;
25081 SPI_MODULE_ID index ) ;
25111 SPI_MODULE_ID index ) ;
25141 SPI_MODULE_ID index ) ;
25171 SPI_MODULE_ID index ) ;
25202 SPI_MODULE_ID index ,
25234 SPI_MODULE_ID index ,
25266 SPI_MODULE_ID index ,
25289 SPI_MODULE_ID index ) ;
25320 SPI_MODULE_ID index ,
25321 SPI_BAUD_RATE_CLOCK type ) ;
25353 SPI_MODULE_ID index ,
25354 SPI_ERROR_INTERRUPT error ) ;
25386 SPI_MODULE_ID index ,
25387 SPI_ERROR_INTERRUPT error ) ;
25418 SPI_MODULE_ID index ,
25419 SPI_AUDIO_ERROR error ) ;
25450 SPI_MODULE_ID index ,
25451 SPI_AUDIO_ERROR error ) ;
25481 SPI_MODULE_ID index ) ;
25511 SPI_MODULE_ID index ) ;
25543 SPI_MODULE_ID index ,
25544 SPI_AUDIO_TRANSMIT_MODE mode ) ;
25576 SPI_MODULE_ID index ,
25577 SPI_AUDIO_PROTOCOL mode ) ;
25610 SPI_MODULE_ID index ) ;
25636 SPI_MODULE_ID index ) ;
25662 SPI_MODULE_ID index ) ;
25687 SPI_MODULE_ID index ) ;
25712 SPI_MODULE_ID index ) ;
25737 SPI_MODULE_ID index ) ;
25763 SPI_MODULE_ID index ) ;
25788 SPI_MODULE_ID index ) ;
25813 SPI_MODULE_ID index ) ;
25838 SPI_MODULE_ID index ) ;
25863 SPI_MODULE_ID index ) ;
25888 SPI_MODULE_ID index ) ;
25914 SPI_MODULE_ID index ) ;
25939 SPI_MODULE_ID index ) ;
25964 SPI_MODULE_ID index ) ;
25989 SPI_MODULE_ID index ) ;
26015 SPI_MODULE_ID index ) ;
26041 SPI_MODULE_ID index ) ;
26067 SPI_MODULE_ID index ) ;
26091 SPI_MODULE_ID index ) ;
26116 SPI_MODULE_ID index ) ;
26141 SPI_MODULE_ID index ) ;
26166 SPI_MODULE_ID index ) ;
26192 SPI_MODULE_ID index ) ;
26217 SPI_MODULE_ID index ) ;
26242 SPI_MODULE_ID index ) ;
26267 SPI_MODULE_ID index ) ;
26292 SPI_MODULE_ID index ) ;
26317 SPI_MODULE_ID index ) ;
26343 SPI_MODULE_ID index ) ;
26370 SPI_MODULE_ID index ) ;
26395 SPI_MODULE_ID index ) ;
26421 SPI_MODULE_ID index ) ;
26447 SPI_MODULE_ID index ) ;
26473 SPI_MODULE_ID index ) ;
26498 SPI_MODULE_ID index ) ;
26523 SPI_MODULE_ID index ) ;
26549 SPI_MODULE_ID index ) ;
26575 SPI_MODULE_ID index ) ;
26587 #include "system/common/sys_common.h" 26588 #include "system/common/sys_module.h" 26589 #include "system/int/sys_int.h" 26590 #include "system/clk/sys_clk.h" 26591 #include "C:\microchip\harmony\v2_06\framework\system\ports\sys_ports.h" 26629 #define DRV_SPI_BUFFER_HANDLE_INVALID ( ( DRV_SPI_BUFFER_HANDLE ) ( - 1 ) ) 26641 #define DRV_SPI_INDEX_0 0 26642 #define DRV_SPI_INDEX_1 1 26643 #define DRV_SPI_INDEX_2 2 26644 #define DRV_SPI_INDEX_3 3 26645 #define DRV_SPI_INDEX_4 4 26646 #define DRV_SPI_INDEX_5 5 26658 #define DRV_SPI_INDEX_COUNT SPI_NUMBER_OF_MODULES 26907 SPI_MODULE_ID
spiId ;
26940 CLK_BUSES_PERIPHERAL
spiClk ;
27100 const SYS_MODULE_INDEX index ,
27101 const SYS_MODULE_INIT *
const init ) ;
27143 SYS_MODULE_OBJ
object ) ;
27192 SYS_MODULE_OBJ
object ) ;
27233 SYS_MODULE_OBJ
object ) ;
27298 const SYS_MODULE_INDEX drvIndex ,
27893 #include "driver/usb/usbhs/drv_usbhs.h" 27894 #include "usb/usb_device.h" 27922 #include <stdint.h> 27942 uint8_t RevNumber ;
28029 SYS_MODULE_OBJ sysTmr ;
28030 SYS_MODULE_OBJ drvTmr0 ;
28031 SYS_MODULE_OBJ drvTmr1 ;
28032 SYS_MODULE_OBJ drvTmr2 ;
28033 SYS_MODULE_OBJ drvTmr3 ;
28034 SYS_MODULE_OBJ drvTmr4 ;
28035 SYS_MODULE_OBJ drvUsart0 ;
28036 SYS_MODULE_OBJ drvPMP0 ;
28038 SYS_MODULE_OBJ spiObjectIdx0 ;
28040 SYS_MODULE_OBJ spiObjectIdx1 ;
28042 SYS_MODULE_OBJ spiObjectIdx2 ;
28043 SYS_MODULE_OBJ drvUSBObject ;
28044 SYS_MODULE_OBJ usbDevObject0 ;
28092 int8_t v_adj [ 1 ] ;
28094 uint16_t voltage_limit ;
28096 uint16_t max_current ;
28097 uint8_t current_limit ;
28098 uint8_t upper_current_limit ;
28099 uint8_t over_current_count ;
28102 bool new_voltage_flag ;
28103 bool new_current_flag ;
28104 bool spi_write_complete_flag ;
28105 bool spi_sent_flag ;
28106 uint8_t avg_count ;
28107 uint8_t avg_count_max ;
28108 uint16_t current_array [ 5 ] ;
28109 uint16_t avg_current ;
28110 uint8_t overvoltage_count ;
28315 #include "../system_config.h" 28316 #include "../system_definitions.h" 28317 #include <stdbool.h> 28326 #define NEGATIVE_OFFSET 0x02U 28327 #define POS_HIGH_OFFSET 0x01U 28328 #define POS_LOW_OFFSET 0x03U 28329 #define DEFAULT_OFFSET 0x04U 28330 #define I_ARRAY_SIZE 50U 28377 uint16_t voltage_limit ;
28378 uint16_t upper_voltage_limit ;
28379 uint16_t volt_count ;
28381 uint16_t max_current ;
28382 uint16_t current_limit ;
28383 uint16_t upper_current_limit ;
28384 uint8_t over_current_count ;
28385 uint8_t array_sum_count ;
28386 uint8_t array_count ;
28388 int16_t i_array [ 50U ] ;
28390 bool new_current_values_flag ;
28391 bool new_voltage_values_flag ;
28392 bool overcurrent_flag ;
28393 bool overvoltage_flag ;
28394 uint16_t sensor_offset ;
28395 uint16_t sensor_constant ;
28396 bool sensor_offset_tick ;
28397 uint16_t v_array [ 50 ] ;
28398 uint16_t v_array_count ;
28404 uint8_t overvoltage_count ;
28535 #include <stdbool.h> 28536 #include <stdint.h> 28568 uint8_t bitposn ) ;
28594 uint8_t bitposn ) ;
28683 #ifndef COMMMODULE_H 28684 #define COMMMODULE_H 28690 #include "../system_definitions.h" 28832 #include "../system_config.h" 28833 #include "../system_definitions.h" 28878 uint8_t null_count ;
28879 bool send_message_complete_flag ;
28886 uint8_t table_count ;
28898 uint8_t byte [ 4 ] ;
28918 uint8_t identifier ;
28920 uint8_t msg_length ;
28921 uint8_t xmit_ready_flag ;
29006 static const uint8_t
29008 { 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U ,
29009 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U
29010 , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U ,
29011 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U
29012 , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U ,
29013 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U
29014 , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U ,
29015 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU
29016 , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU ,
29017 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U
29018 , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U } ;
29020 static const uint8_t
29022 { 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U ,
29023 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U
29024 , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U ,
29025 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U
29026 , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U , 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U , 0x7FU , 0x99U , 0xB1U ,
29027 0xC6U , 0xD6U , 0xE0U , 0xE3U , 0xE0U , 0xD6U , 0xC6U , 0xB1U , 0x99U , 0x80U , 0x66U , 0x4EU , 0x39U , 0x29U , 0x1FU , 0x1BU , 0x1EU , 0x28U , 0x38U , 0x4CU , 0x65U } ;
29063 uint8_t Identifier ,
29065 uint8_t Msg_Length ) ;
29278 #include <stdbool.h> 29279 #include "../system_config.h" 29280 #include "../system_definitions.h" 29296 #define ManHalfUpper 11800U 29297 #define ManHalfLower 2000U 29298 #define ManFullUpper 20000U 29299 #define ManFullLower 11801U 29300 #define NoManBits 32U 29301 #define HalfBit 0x12U 29302 #define FullBit 0x10U 29303 #define SizeOfBiasLUT 48U 29383 uint16_t preamble [ 5 ] ;
29384 uint16_t time [ 96 ] ;
29385 uint8_t level [ 96 ] ;
29386 uint8_t ans [ 32U + 2 ] ;
29387 uint8_t msg [ 4 ] ;
29388 uint8_t cnt_preamble ;
29389 uint8_t trynumber ;
29390 bool process_complete_flag ;
29391 bool spi_write_complete_flag ;
29392 bool spi_sent_flag ;
29393 uint8_t timer_count ;
29394 uint8_t timer_complete ;
29398 bool manual_bias_flag ;
29421 uint16_t adj [ 1 ] ;
29422 uint16_t dac_a_setting ;
29423 uint16_t dac_b_setting ;
29815 #include <stdint.h> 29816 #include <stdbool.h> 29822 #define S3_NUM_OF_POSITIONS 5U 29823 #define S6_NUM_OF_POSITIONS 3U 29824 #define S4_NUM_OF_POSITIONS 2U 29825 #define S1_NUM_OF_POSITIONS 2U 29865 uint8_t knob_switch_S3 [ 5 ] ;
29866 uint8_t key_switch_S6 [ 3 ] ;
29867 uint8_t pol_switch_S4 [ 2 ] ;
29868 uint8_t dump_fire_switch_S7 ;
29869 uint8_t fire_switch_S1 [ 2 ] ;
29870 uint8_t hvps_switch_S5 ;
29875 uint16_t store_buffer [ 2 ] ;
29876 uint16_t settings ;
29877 uint8_t dump_fire_count ;
29878 bool debounce_flag ;
29879 bool debounce_tick ;
29983 bool dmpfire_flag ;
30159 #include "../system_config.h" 30160 #include "../system_definitions.h" 30161 #include <stdbool.h> 30167 #define I_ARRAY_SIZE 50U 30212 uint16_t voltage_limit ;
30213 uint16_t upper_voltage_limit ;
30214 uint16_t volt_count ;
30216 uint16_t max_current ;
30217 uint16_t current_limit ;
30218 uint16_t upper_current_limit ;
30219 uint8_t over_current_count ;
30220 uint8_t array_count ;
30221 int16_t i_array [ 50U ] ;
30223 bool new_current_values_flag ;
30224 bool new_voltage_values_flag ;
30225 bool overcurrent_flag ;
30226 bool overvoltage_flag ;
30227 uint16_t sensor_offset ;
30228 uint16_t sensor_constant ;
30229 bool sensor_offset_tick ;
30230 uint16_t v_array [ 50 ] ;
30236 uint8_t overvoltage_count ;
30304 #include "../system_definitions.h" 30354 bool spi_write_complete_flag ;
30355 bool spi_sent_flag ;
30356 uint16_t adj [ 1 ] ;
30359 bool new_cont_values_flag ;
30361 uint16_t cont_prev ;
30362 uint16_t cont_new ;
30366 uint16_t update_rate ;
30367 uint16_t rate_time ;
30368 uint16_t update_count ;
30372 uint16_t sensor_offset ;
30374 uint16_t sensor_constant ;
30375 uint16_t max_current ;
30376 uint16_t current_limit ;
30377 uint16_t upper_current_limit ;
30378 uint8_t over_current_count ;
30379 bool new_current_values_flag ;
30380 bool new_voltage_values_flag ;
30381 bool overcurrent_flag ;
30382 bool overvoltage_flag ;
30458 #include <string.h> 30459 #include <stdbool.h> 30467 #define Set_WL_SPS_CurrentLimit_Value 0x30U 30468 #define Get_WL_SPS_CurrentLimit 0x31U 30469 #define Set_HVPS_Ramp_Rate_Value 0x32U 30470 #define HVPS_Supply_On 0x33U 30471 #define HVPS_Supply_Off 0x34U 30472 #define APA_COM_6 0x35U 30473 #define APA_COM_7 0x36U 30474 #define APA_COM_8 0x37U 30475 #define APA_COM_9 0x38U 30476 #define APA_COM_10 0x39U 30477 #define APA_COM_11 0x3AU 30478 #define APA_COM_12 0x3BU 30479 #define APA_COM_13 0x3CU 30480 #define APA_COM_14 0x3DU 30481 #define APA_COM_15 0x3EU 30482 #define APA_COM_16 0x3FU 30483 #define APA_COM_17 0x40U 30484 #define APA_COM_18 0x41U 30485 #define APA_COM_19 0x43U 30486 #define APA_COM_20 0x44U 30487 #define APA_COM_21 0x45U 30490 #define Set_WL_CPS_CurrentLimit_Value 0x50U 30491 #define Get_WL_CPS_Current 0x51U 30492 #define Get_WL_CPS_CurrentMax 0x52U 30493 #define Get_WL_CPS_CurrentLimit 0x53U 30494 #define Set_WL_CPS_Voltage 0x54U 30495 #define WL_CPS_Off 0x55U 30496 #define WL_CPS_On 0x56U 30497 #define Get_WL_CPS_Voltage 0x57U 30498 #define Set_MAN_Bias_Auto 0x58U 30499 #define Set_MAN_Bias_Manual 0x59U 30500 #define Get_MAN_Bias 0x5AU 30501 #define Get_PIB_Revision 0x5BU 30502 #define Get_PIB_Status 0x5CU 30503 #define Get_FP_Switch_Settings 0x5DU 30504 #define Close_COMM_Relay 0x5EU 30505 #define Open_COMM_Relay 0x5FU 30506 #define SetK1Log 0x60U 30507 #define SetK1Perf 0x61U 30508 #define Get_WL_SPS_I_V 0x62U 30509 #define Get_WL_CPS_I_V 0x63U 30510 #define PA_COM_21 0x64U 30511 #define Initialize 0x65U 30512 #define SetK2Log 0x66U 30513 #define SetK2Perf 0x67U 30514 #define PA_COM_22 0x68U 30515 #define PA_COM_23 0x69U 30516 #define PA_COM_24 0x6AU 30517 #define PA_COM_25 0x6BU 30518 #define PA_COM_26 0x6CU 30519 #define PA_COM_27 0x6DU 30520 #define PA_COM_28 0x6EU 30521 #define PA_COM_29 0x6FU 30522 #define PA_COM_30 0x70U 30525 #define Short_Message30mA 0x80U 30526 #define Switch_WL_ON_Hibernate 0x81U 30527 #define Switch_ARM 0x82U 30528 #define SS_WL_FET_1_ON 0x83U 30529 #define LongMessage 0x84U 30530 #define SS_WL_FET_1_OFF 0x85U 30531 #define SS_WL_FET_2_ON 0x86U 30532 #define SS_WL_FET_2_OFF 0x87U 30533 #define Switch_Fire_12sec 0x88U 30534 #define Switch_Fire_30sec 0x89U 30535 #define Get_Switch_Rev 0x8AU 30536 #define Get_SS_Temp 0x8BU 30537 #define Short_Message10mA 0x8CU 30538 #define Get_Voltage 0x8DU 30539 #define SS_WL_FET_3_ON 0x8EU 30540 #define SS_WL_FET_3_OFF 0x8FU 30541 #define SS_WL_FET_4_ON 0x90U 30542 #define SS_WL_FET_4_OFF 0x91U 30543 #define Open_Mot_Rel_Tool 0x92U 30544 #define Close_Mot_Rel_Tool 0x93U 30545 #define PB_COM_16 0x94U 30546 #define Get_Device_Type 0x95U 30547 #define Get_Det_Detect 0x96U 30548 #define Switch_Fire_120sec 0x97U 30549 #define PB_COM_20 0x98U 30550 #define PB_COM_21 0x99U 30551 #define PB_COM_22 0x9AU 30552 #define PB_COM_23 0x9BU 30553 #define PB_COM_24 0x9CU 30554 #define PB_COM_25 0x9DU 30555 #define PB_COM_26 0x9EU 30556 #define PB_COM_27 0x9FU 30557 #define PB_COM_28 0xA0U 30558 #define PB_COM_29 0xA1U 30559 #define PB_COM_30 0xA2U 30560 #define PB_COM_31 0xA3U 30561 #define PB_COM_32 0xA4U 30562 #define PB_COM_33 0xA5U 30563 #define PB_COM_34 0xA6U 30564 #define PB_COM_35 0xA7U 30565 #define PB_COM_36 0xA8U 30566 #define PB_COM_37 0xA9U 30567 #define PB_COM_38 0xAAU 30568 #define PB_COM_39 0xABU 30569 #define PB_COM_40 0xACU 30570 #define PB_COM_41 0xADU 30571 #define PB_COM_42 0xAEU 30572 #define PB_COM_43 0xAFU 30573 #define Command_Wait 0xB0U 30575 #define NoOfCommands 103 30626 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 28)));
30839 int izzqqzz=((int)(
bitmapstruct.element3 |= (1 << 4)));
30939 int izzqqzz=((int)(
bitmapstruct.element3 |= (1 << 21)));
31419 int izzqqzz=((int)(
bitmapstruct.element6 |= (1 << 13)));
31456 ident = ident | 0x08U ;
31467 ident = ident | 0x08U ;
31478 ident = ident | 0x08U ;
31489 ident = ident | 0x08U ;
31500 ident = ident | 0x08U ;
31511 ident = ident | 0x08U ;
31522 ident = ident | 0x08U ;
31533 ident = ident | 0x08U ;
31544 ident = ident | 0x08U ;
31556 ident = ident | 0x08U ;
31568 ident = ident | 0x08U ;
31580 ident = ident | 0x08U ;
31591 ident = ident | 0x08U ;
31602 ident = ident | 0x08U ;
31613 ident = ident | 0x08U ;
31624 ident = ident | 0x08U ;
31635 ident = ident | 0x08U ;
31646 ident = ident | 0x08U ;
31658 ident = ident | 0x08U ;
31670 ident = ident | 0x08U ;
31681 ident = ident | 0x08U ;
31693 ident = ident | 0x08U ;
31705 ident = ident | 0x08U ;
31717 ident = ident | 0x08U ;
31729 ident = ident | 0x08U ;
31741 ident = ident | 0x08U ;
31753 ident = ident | 0x08U ;
31765 ident = ident | 0x08U ;
31775 ident = ident | 0x08U ;
31800 int izzqqzz=((int)(
bitmapstruct.element8 |= (1 << 14)));
31863 int izzqqzz=((int)(
bitmapstruct.element8 |= (1 << 27)));
31883 int izzqqzz=((int)(
bitmapstruct.element8 |= (1 << 29)));
31888 CommandBitMap [ 103 ] = { 0x30U , 0x31U , 0x32U , 0x33U , 0x34U , 0x35U ,
31889 0x36U , 0x37U , 0x38U , 0x39U , 0x3AU , 0x3BU , 0x3CU , 0x3DU , 0x3EU , 0x3FU , 0x40U , 0x41U , 0x42U , 0x43U , 0x44U , 0x45U , 0x50U , 0x51U , 0x52U , 0x53U , 0x54U , 0x55U , 0x56U , 0x57U , 0x58U , 0x59U ,
31890 0x5AU , 0x5BU , 0x5CU , 0x5DU , 0x5EU , 0x5FU , 0x60U , 0x61U , 0x62U , 0x63U , 0x64U , 0x65U , 0x66U , 0x67U , 0x68U , 0x69U , 0x6AU , 0x6BU , 0x6CU , 0x6DU , 0x6FU , 0x70U , 0x80U , 0x81U , 0x82U , 0x83U ,
31891 0x84U , 0x85U , 0x86U , 0x87U , 0x88U , 0x89U , 0x8AU , 0x8BU , 0x8CU , 0x8DU , 0x8EU , 0x8FU , 0x90U , 0x91U , 0x92U , 0x93U , 0x94U , 0x95U , 0x96U , 0x97U , 0x98U , 0x99U , 0x9AU , 0x9BU , 0x9CU , 0x9DU ,
31892 0x9EU , 0x9FU , 0xA0U , 0xA1U , 0xA2U , 0xAU , 0xA4U , 0xA5U , 0xA6U , 0xA7U , 0xA8U , 0xA9U , 0xAAU , 0xABU , 0xACU , 0xADU , 0xAEU , 0xAFU , 0xB0U } ;
31901 (
char * ) CommandBitMap , msg ) != NULL
31931 #define qqqbranches 292 31932 #define QQQMAXMCDCSIZE 2 31936 #define ldra_sscanf 31952 #undef qqnull_params 31953 #define qqnull_params void 31955 #define qqzzidfield 1 31961 #define QQQFIXEDSIZE 31981 qqcptr = qqscan_str;
31983 while (qqcptr[0] ==
' ')
31989 if (qqcptr[0] ==
'-')
31995 while ((qqcptr[0] >=
'0') && (qqcptr[0] <=
'9'))
31997 qqvalue = 10 * qqvalue;
31998 qqvalue = qqvalue + (qqcptr[0] -
'0');
32001 qqvalue = qqisign * qqvalue;
32027 ldra_sprintf2 (&ldra_buffer[0], s,i,
zzfileid);
32028 ldra_port_write (&ldra_buffer[0]);
32036 ldra_port_write(s);
32044 ldra_sprintf2 (&ldra_buffer[0], s, i, j);
32045 ldra_port_write (&ldra_buffer[0]);
32053 ldra_sprintf3 (&ldra_buffer[0], s, i, j, k);
32054 ldra_port_write (&ldra_buffer[0]);
32062 ldra_sprintf4 (&ldra_buffer[0], s, i, j, k, l);
32063 ldra_port_write (&ldra_buffer[0]);
32182 static int branches_printed = 0;
32186 ldra_sprintf1 (&ldra_buffer[0], s, (i >> last) & ~(~0 << 8));
32187 ldra_port_write (&ldra_buffer[0]);
32188 ldra_sprintf1 (&ldra_buffer[0],
"%8d\n",
zzfileid );
32189 ldra_port_write (&ldra_buffer[0]);
32191 branches_printed += 8;
32211 #define ELEMENT(N) qqbmsoutput("%8d", bitmapstruct.element##N); 32212 #define LASTELEMENT 32213 #include "commands_65zbelem.def" uint32_t DRV_TMR1_PeriodValueGet(void)
uint16_t PLIB_DMA_ChannelXPeripheralAddressGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsOutputDataPhase(SPI_MODULE_ID index)
void PLIB_USART_BaudSetAndEnable(USART_MODULE_ID index, uint32_t systemClock, uint32_t baud)
bool PLIB_USART_ExistsTransmitterBreak(USART_MODULE_ID index)
bool PLIB_PORTS_ExistsLatchRead(PORTS_MODULE_ID index)
void SYS_DMA_ChannelTransferEventHandlerSet(SYS_DMA_CHANNEL_HANDLE handle, const SYS_DMA_CHANNEL_TRANSFER_EVENT_HANDLER eventHandler, const uintptr_t contextHandle)
void DRV_ADC0_Close(void)
bool PLIB_PORTS_PinGetLatched(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_PORTS_ChannelChangeNoticeDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_DMA_CRCWriteByteOrderMaintain(DMA_MODULE_ID index)
#define DRV_IC_Close(handle)
SPI_BAUD_RATE_CLOCK baudClockSource
static void DRV_TMR1_DeInitialize(void)
void Calc_CRC(uint16_t nbits, uint8_t thebits)
void PLIB_SPI_ReceiverOverflowClear(SPI_MODULE_ID index)
void SYS_DMA_ChannelRelease(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_DMA_ChannelXNullWriteModeIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
void * PLIB_SPI_BufferAddressGet(SPI_MODULE_ID index)
void SYS_PORTS_PinModeSelect(PORTS_MODULE_ID index, PORTS_ANALOG_PIN pin, PORTS_PIN_MODE mode)
void PLIB_USART_Enable(USART_MODULE_ID index)
SYS_DMA_CHANNEL_HANDLE SYS_DMA_ChannelAllocate(DMA_CHANNEL channel)
uint32_t PLIB_DMA_CRCXOREnableGet(DMA_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXSourcePointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool Valid_Command(uchar8_t msg)
DRV_USART_LINE_CONTROL_SET_RESULT DRV_USART_LineControlSet(const DRV_HANDLE client, const DRV_USART_LINE_CONTROL lineControl)
bool PLIB_DMA_ExistsChannelXAuto(DMA_MODULE_ID index)
uint32_t DRV_TMR0_CounterFrequencyGet(void)
void PLIB_USART_IrDADisable(USART_MODULE_ID index)
uint32_t DRV_TMR1_CounterFrequencyGet(void)
void PLIB_DMA_ChannelXChainToLower(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_SPI_CommunicationWidthSelect(SPI_MODULE_ID index, SPI_COMMUNICATION_WIDTH width)
bool PLIB_SPI_FIFOShiftRegisterIsEmpty(SPI_MODULE_ID index)
uint8_t DRV_USART_ReadByte(const DRV_HANDLE handle)
void PLIB_USART_RunInOverflowDisable(USART_MODULE_ID index)
uint32_t PLIB_SPI_BufferRead32bit(SPI_MODULE_ID index)
TMR_PRESCALE DRV_TMR3_PrescalerGet(void)
void DRV_USART_BufferEventHandlerSet(const DRV_HANDLE handle, const DRV_USART_BUFFER_EVENT_HANDLER eventHandler, const uintptr_t context)
void SYS_PORTS_Toggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK toggleMask)
static int commands_65zscanf(char *qqscan_str)
void DRV_TMR_AlarmPeriodSet(DRV_HANDLE handle, uint32_t value)
void PLIB_DMA_CRCAppendModeEnable(DMA_MODULE_ID index)
DRV_USART_LINE_CONTROL_SET_RESULT
PORTS_PIN_SLEW_RATE PLIB_PORTS_PinSlewRateGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_PORTS_RemapOutput(PORTS_MODULE_ID index, PORTS_REMAP_OUTPUT_FUNCTION outputFunction, PORTS_REMAP_OUTPUT_PIN remapOutputPin)
void SYS_PORTS_PinPullUpDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void Set_Status(uint8_t bitposn)
void DRV_PMP0_Write(uint8_t data)
bool PLIB_DMA_ExistsStartTransfer(DMA_MODULE_ID index)
void DRV_TMR0_CounterClear(void)
SPI_FRAME_PULSE_POLARITY framePulsePolarity
bool PLIB_PORTS_ExistsSlewRateControl(PORTS_MODULE_ID index)
bool DRV_TMR_GateModeSet(DRV_HANDLE handle)
void PLIB_USART_OperationModeSelect(USART_MODULE_ID index, USART_OPERATION_MODE operationmode)
void DRV_ADC1_Close(void)
bool PLIB_PORTS_ExistsAnPinsMode(PORTS_MODULE_ID index)
bool PLIB_DMA_ExistsRecentAddress(DMA_MODULE_ID index)
void PLIB_PORTS_DirectionOutputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
static void Init_WL_CPS(void)
bool PLIB_DMA_ChannelXChainIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_USART_AddressedBufferAddWrite(const DRV_HANDLE hClient, DRV_USART_BUFFER_HANDLE *bufferHandle, uint8_t address, void *source, size_t nWords)
static void Execute_Protocol_B(void)
void SYS_PORTS_PinClear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_PORTS_ChangeNoticeEnable(PORTS_MODULE_ID index)
void DRV_TMR4_PeriodValueSet(uint32_t value)
static void DRV_TMR2_Close(void)
bool PLIB_USART_RunInOverflowIsEnabled(USART_MODULE_ID index)
DMA_PING_PONG_MODE PLIB_DMA_ChannelXPingPongModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool SYS_PORTS_PinLatchedGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_USART_ExistsReceiverFramingErrorStatus(USART_MODULE_ID index)
static void Execute_Protocol_A(void)
uint32_t DRV_TMR0_CounterValueGet(void)
bool PLIB_USART_ExistsTransmitterInterruptMode(USART_MODULE_ID index)
void PLIB_USART_InitializeModeGeneral(USART_MODULE_ID index, bool autobaud, bool loopBackMode, bool wakeFromSleep, bool irdaMode, bool stopInIdle)
void DRV_TMR3_Initialize(void)
void PLIB_SPI_FrameErrorStatusClear(SPI_MODULE_ID index)
static DRV_TMR_OPERATION_MODE DRV_TMR3_OperationModeGet(void)
void PLIB_DMA_ChannelXStartAddressOffsetSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t address, DMA_ADDRESS_OFFSET_TYPE offset)
bool PLIB_DMA_ChannelXEventIsDetected(DMA_MODULE_ID index, DMA_CHANNEL channel)
void SYS_DMA_ChannelTransferSet(SYS_DMA_CHANNEL_HANDLE handle, const void *srcAddr, size_t srcSize, const void *destAddr, size_t destSize, size_t cellSize)
void SYS_PORTS_ChangeNotificationPullUpDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
DRV_USART_LINE_CONTROL_SET_RESULT
void Prepare_Return_B(uint8_t byt [])
DMA_CHANNEL_INT_SOURCE PLIB_DMA_ChannelXTriggerSourceNumberGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_USART_TransmitterIdleIsLowEnable(USART_MODULE_ID index)
void PLIB_SPI_AudioCommunicationWidthSelect(SPI_MODULE_ID index, SPI_AUDIO_COMMUNICATION_WIDTH mode)
void PLIB_DMA_ChannelXReloadEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_PORTS_ChannelChangeNoticeEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_DMA_ChannelXDestinationAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_DESTINATION_ADDRESSING_MODE destinationAddressMode)
void PLIB_USART_TransmitterBreakSend(USART_MODULE_ID index)
void SYS_PORTS_OpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
static void DRV_TMR2_Tasks(void)
void DRV_TMR_Stop(DRV_HANDLE handle)
bool PLIB_DMA_ExistsChannelXAbortIRQ(DMA_MODULE_ID index)
DRV_USART_TRANSFER_STATUS DRV_USART0_TransferStatus(void)
static void Init_Manchester(void)
bool PLIB_DMA_IsEnabled(DMA_MODULE_ID index)
#define commands_65zqqzqz1
void PLIB_DMA_ChannelXINTSourceFlagClear(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
bool PLIB_SPI_ExistsFrameSyncPulseWidth(SPI_MODULE_ID index)
bool PLIB_USART_ExistsBRGClockSourceSelect(USART_MODULE_ID index)
bool PLIB_DMA_ExistsCRC(DMA_MODULE_ID index)
void DRV_USART_BufferAddRead(const DRV_HANDLE handle, DRV_USART_BUFFER_HANDLE *const bufferHandle, void *buffer, const size_t size)
void SET_WL_SPS_IOffset(uint8_t mode)
bool PLIB_SPI_ExistsFIFOCount(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXCellProgressPointer(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXPatternDataSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t patternData)
bool PLIB_USART_ExistsReceiverEnable(USART_MODULE_ID index)
SYS_MODULE_OBJ DRV_USART_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
SYS_STATUS DRV_SPI_Status(SYS_MODULE_OBJ object)
bool PLIB_PORTS_ExistsPinChangeNoticePerPort(PORTS_MODULE_ID index)
DRV_TMR_OPERATION_MODE DRV_TMR1_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
bool DRV_USART0_ReceiverBufferIsEmpty(void)
void PLIB_DMA_ChannelXPatternIgnoreByteDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_USART_WakeOnStartEnable(USART_MODULE_ID index)
void PLIB_DMA_CRCByteOrderSelect(DMA_MODULE_ID index, DMA_CRC_BYTE_ORDER byteOrder)
DRV_USART_BAUD_SET_RESULT
bool PLIB_DMA_ChannelXINTSourceIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
bool PLIB_PORTS_PinGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
SYS_STATUS DRV_TMR_Status(SYS_MODULE_OBJ object)
DMA_CHANNEL_PRIORITY PLIB_DMA_ChannelPriorityGet(DMA_MODULE_ID index)
SYS_MODULE_OBJ DRV_IC_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
#define DRV_IC_Open(drvIndex, intent)
void PLIB_PORTS_ChannelChangeNoticePullUpDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_DMA_ExistsChannelXDestinationSize(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXSourceStartAddressSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint32_t sourceStartAddress)
uint32_t PLIB_DMA_ChannelXSourceStartAddressGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool PLIB_USART_ExistsHandshakeMode(USART_MODULE_ID index)
bool PLIB_USART_ExistsStopInIdle(USART_MODULE_ID index)
void DRV_TMR1_CounterValueSet(uint32_t value)
void qqpopulate_array_fcn_ptrQQ(int x, ldra_void_function y, ldra_void_function z)
bool PLIB_DMA_ExistsChannelXINTSource(DMA_MODULE_ID index)
USART_ERROR PLIB_USART_ErrorsGet(USART_MODULE_ID index)
static void Init_FSK(void)
bool PLIB_SPI_ExistsPinControl(SPI_MODULE_ID index)
uint32_t DRV_TMR3_CounterValueGet(void)
uint8_t jobQueueReserveSize
void PLIB_USART_RunInOverflowEnable(USART_MODULE_ID index)
bool PLIB_PORTS_ExistsRemapOutput(PORTS_MODULE_ID index)
bool PLIB_USART_ExistsReceiverParityErrorStatus(USART_MODULE_ID index)
void PLIB_SPI_BaudRateClockSelect(SPI_MODULE_ID index, SPI_BAUD_RATE_CLOCK type)
uint32_t DRV_TMR4_PeriodValueGet(void)
void SYS_DEBUG_Reinitialize(SYS_MODULE_OBJ object, const SYS_MODULE_INIT *const init)
SYS_MODULE_INIT moduleInit
void DRV_TMR2_StopInIdleDisable(void)
void PLIB_PORTS_ChangeNoticePullDownPerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_DMA_ChannelXTransferDirectionSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRANSFER_DIRECTION chTransferDirection)
static DRV_TMR_OPERATION_MODE DRV_TMR0_OperationModeGet(void)
void SYS_PORTS_PinPullUpEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
ldra_void_function qqqaccumupload[QQQnumfil]
DRV_TMR_OPERATION_MODE DRV_TMR0_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
void PLIB_PORTS_ChangeNoticePerPortTurnOn(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_DMA_ExistsChannelXPatternData(DMA_MODULE_ID index)
void DRV_USART_ByteTransmitCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
void PLIB_DMA_ChannelXINTSourceDisable(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
bool PLIB_PORTS_ExistsChangeNoticePerPortStatus(PORTS_MODULE_ID index)
int8_t PLIB_USART_ReceiverByteReceive(USART_MODULE_ID index)
static void qqoutput0(FILEPOINT char *s)
bool PLIB_DMA_ExistsCRCPolynomialLength(DMA_MODULE_ID index)
void Calc_Auto_Bias(void)
uint8_t PLIB_DMA_ChannelXPatternIgnoreGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
uintptr_t DRV_SPI_BUFFER_HANDLE
void PLIB_SPI_ErrorInterruptDisable(SPI_MODULE_ID index, SPI_ERROR_INTERRUPT error)
static int qqqisinitialised
void DRV_USART0_Deinitialize(void)
bool send_message_complete_flag
void DRV_USART_Close(const DRV_HANDLE handle)
static void DRV_TMR2_Open(void)
SYS_PORTS_PULLUP_PULLDOWN_STATUS
void PLIB_DMA_CRCEnable(DMA_MODULE_ID index)
bool DRV_IC0_BufferIsEmpty(void)
void PLIB_USART_LineControlModeSelect(USART_MODULE_ID index, USART_LINECONTROL_MODE dataFlowConfig)
static void DRV_TMR1_Open(void)
bool spi_write_complete_flag
bool PLIB_PORTS_ExistsPinMode(PORTS_MODULE_ID index)
static void Send_Mark(void)
void PLIB_SPI_FramedCommunicationDisable(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXAbortIRQSet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRIGGER_SOURCE IRQ)
void PLIB_SPI_FrameSyncPulseDirectionSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_DIRECTION direction)
bool DRV_TMR1_Start(void)
void PLIB_USART_LoopbackDisable(USART_MODULE_ID index)
void SYS_DMA_ChannelSetupMatchAbortMode(SYS_DMA_CHANNEL_HANDLE handle, uint16_t pattern, DMA_PATTERN_LENGTH length, SYS_DMA_CHANNEL_IGNORE_MATCH ignore, uint8_t ignorePattern)
void PLIB_DMA_CRCChannelSelect(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_PORTS_PinChangeNoticeEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
static void execute_switches(void)
void PLIB_USART_WakeOnStartDisable(USART_MODULE_ID index)
void SYS_PORTS_ChangeNotificationInIdleModeEnable(PORTS_MODULE_ID index)
void PLIB_USART_ReceiverAddressAutoDetectEnable(USART_MODULE_ID index, int8_t Mask)
void PLIB_PORTS_OpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_DMA_Enable(DMA_MODULE_ID index)
void DRV_TMR1_CounterClear(void)
bool PLIB_USART_ModuleIsBusy(USART_MODULE_ID index)
void PLIB_DMA_CRCTypeSet(DMA_MODULE_ID index, DMA_CRC_TYPE CRCType)
INT_SOURCE txInterruptSource
bool PLIB_USART_TransmitterBufferIsFull(USART_MODULE_ID index)
void PLIB_DMA_BusyActiveSet(DMA_MODULE_ID index)
DMA_SOURCE_ADDRESSING_MODE PLIB_DMA_ChannelXSourceAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint32_t DRV_TMR1_CounterValueGet(void)
void(* DRV_USART_BYTE_EVENT_HANDLER)(const SYS_MODULE_INDEX index)
DMA_CHANNEL_DATA_SIZE PLIB_DMA_ChannelXDataSizeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
DRV_HANDLE DRV_IC_Start(const SYS_MODULE_INDEX drvIndex, const DRV_IO_INTENT intent)
void SYS_DEBUG_Message(const char *message)
void PLIB_DMA_ChannelXNullWriteModeEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
static unsigned char qqqzzglobflag
bool PLIB_USART_RunInSleepModeIsEnabled(USART_MODULE_ID index)
bool PLIB_SPI_ReceiverHasOverflowed(SPI_MODULE_ID index)
bool PLIB_PORTS_ExistsRemapInput(PORTS_MODULE_ID index)
void DRV_TMR1_StopInIdleEnable(void)
static void DRV_TMR0_Open(void)
void SYS_DMA_ChannelDisable(SYS_DMA_CHANNEL_HANDLE handle)
bool DRV_SPIn_ReceiverBufferIsFull(void)
void DRV_TMR3_CounterClear(void)
USART_BRG_CLOCK_SOURCE PLIB_USART_BRGClockSourceGet(USART_MODULE_ID index)
void SYS_PORTS_Initialize()
void DRV_USART0_WriteByte(const uint8_t byte)
void PLIB_SPI_AudioProtocolEnable(SPI_MODULE_ID index)
bool PLIB_USART_TransmitterBreakSendIsComplete(USART_MODULE_ID index)
DRV_USART_TRANSFER_STATUS
static bool Check_Manchester(void)
void DRV_PMP0_TimingSet(PMP_DATA_WAIT_STATES dataWait, PMP_STROBE_WAIT_STATES strobeWait, PMP_DATA_HOLD_STATES dataHold)
void DRV_SPI_Close(DRV_HANDLE handle)
void DRV_TMR1_StopInIdleDisable(void)
SYS_DMA_CHANNEL_IGNORE_MATCH
static void DRV_TMR4_Open(void)
void PLIB_SPI_AudioProtocolModeSelect(SPI_MODULE_ID index, SPI_AUDIO_PROTOCOL mode)
SPI_FRAME_PULSE_DIRECTION framePulseDirection
void SYS_DMA_ChannelCRCSet(SYS_DMA_CHANNEL_HANDLE handle, SYS_DMA_CHANNEL_OPERATION_MODE_CRC crc)
uint16_t PLIB_DMA_ChannelXTransferCountGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
static void DRV_TMR4_Tasks(void)
bool PLIB_USART_ExistsIrDA(USART_MODULE_ID index)
bool PLIB_SPI_ExistsAudioTransmitMode(SPI_MODULE_ID index)
size_t SYS_DMA_ChannelDestinationTransferredSizeGet(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_USART_ReceiverAddressDetectDisable(USART_MODULE_ID index)
bool PLIB_PORTS_ChangeNoticePerPortHasOccurred(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void SYS_DMA_Suspend(void)
bool PLIB_USART_BaudRateAutoDetectIsComplete(USART_MODULE_ID index)
void SYS_DEBUG_Print(const char *format,...)
uint32_t PLIB_USART_BaudRateGet(USART_MODULE_ID index, int32_t clockFrequency)
bool DRV_TMR4_Start(void)
void PLIB_PORTS_ChangeNoticePullUpEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void PLIB_PORTS_CnPinsPullUpDisable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
void SYS_DMA_ChannelAbortEventSet(SYS_DMA_CHANNEL_HANDLE handle, DMA_TRIGGER_SOURCE eventSrc)
void SYS_PORTS_ChangeNotificationInIdleModeDisable(PORTS_MODULE_ID index)
bool DRV_SPIn_TransmitterBufferIsFull(void)
void PLIB_PORTS_ChangeNoticePullUpPerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void DRV_TMR0_CounterValueSet(uint32_t value)
bool PLIB_DMA_ExistsChannelXSourceSize(DMA_MODULE_ID index)
uint16_t PLIB_SPI_BufferRead16bit(SPI_MODULE_ID index)
DRV_SPI_PROTOCOL_TYPE spiProtocolType
bool PLIB_SPI_ExistsFIFOControl(SPI_MODULE_ID index)
void DRV_TMR4_Initialize(void)
void PLIB_DMA_ChannelPrioritySelect(DMA_MODULE_ID index, DMA_CHANNEL_PRIORITY channelPriority)
bool PLIB_DMA_ExistsCRCChannel(DMA_MODULE_ID index)
void Set_WL_CPS_CurrentLimit(uint8_t value)
static SYS_STATUS DRV_TMR3_Status(void)
SPI_FRAME_PULSE_WIDTH framePulseWidth
void PLIB_PORTS_DirectionInputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_PORTS_ChangeNoticePerPortTurnOff(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void DRV_USART0_TasksTransmit(void)
uint32_t DRV_ADC_SamplesRead(uint8_t bufIndex)
bool PLIB_USART_ExistsRunInSleepMode(USART_MODULE_ID index)
bool PLIB_SPI_IsBusy(SPI_MODULE_ID index)
bool spi_write_complete_flag
static void process_switches(void)
struct _DRV_SPI_INIT DRV_SPI_INIT
void PLIB_DMA_ChannelXSourceAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_SOURCE_ADDRESSING_MODE sourceAddressMode)
void PLIB_DMA_ChannelXDisabledEnablesEvents(DMA_MODULE_ID index, DMA_CHANNEL channel)
static void qqqqinitialise(int ii)
bool SYS_PORTS_PinRead(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DRV_HANDLE DRV_USART0_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT ioIntent)
bool PLIB_DMA_ExistsChannelXChainEnbl(DMA_MODULE_ID index)
SYS_DMA_CHANNEL_IGNORE_MATCH
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddRead(DRV_HANDLE handle, void *rxBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
uint8_t DRV_USART0_ReadByte(void)
static struct bitmapstruct_t bitmapstruct
SYS_MODULE_OBJ DRV_SPI_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
PORTS_DATA_TYPE SYS_PORTS_LatchedGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_SPI_BufferWrite32bit(SPI_MODULE_ID index, uint32_t data)
void SYS_PORTS_InterruptEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_PIN_INTERRUPT_TYPE pinInterruptType)
void PLIB_DMA_ChannelXDestinationStartAddressSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint32_t destinationStartAddress)
bool PLIB_USART_ExistsBaudRate(USART_MODULE_ID index)
bool PLIB_PORTS_ExistsPortsRead(PORTS_MODULE_ID index)
bool PLIB_DMA_LastBusAccessIsWrite(DMA_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWrite(DRV_HANDLE handle, void *txBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
void PLIB_DMA_ChannelXTriggerEnable(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
void DRV_TMR_Deinitialize(SYS_MODULE_OBJ object)
bool PLIB_SPI_ExistsTransmitBufferEmptyStatus(SPI_MODULE_ID index)
bool PLIB_USART_ReceiverDataIsAvailable(USART_MODULE_ID index)
bool PLIB_USART_WakeOnStartIsEnabled(USART_MODULE_ID index)
bool PLIB_SPI_ReceiverFIFOIsEmpty(SPI_MODULE_ID index)
uint32_t PLIB_DMA_CRCDataRead(DMA_MODULE_ID index)
void PLIB_USART_BaudRateAutoDetectEnable(USART_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWrite2(DRV_HANDLE handle, void *txBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
unsigned int DRV_USART_ReceiverBufferSizeGet(const DRV_HANDLE handle)
DRV_SPI_BUFFER_EVENT DRV_SPI_BufferStatus(DRV_SPI_BUFFER_HANDLE bufferHandle)
DMA_PATTERN_LENGTH PLIB_DMA_ChannelXPatternLengthGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void SYS_DMA_ChannelForceAbort(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_SPI_FrameErrorStatusGet(SPI_MODULE_ID index)
void PLIB_SPI_FIFOInterruptModeSelect(SPI_MODULE_ID index, SPI_FIFO_INTERRUPT mode)
bool PLIB_USART_ExistsReceiverAddress(USART_MODULE_ID index)
void SYS_PORTS_ChangeNotificationEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum, SYS_PORTS_PULLUP_PULLDOWN_STATUS value)
static SYS_STATUS DRV_TMR2_Status(void)
void PLIB_PORTS_PinModeSelect(PORTS_MODULE_ID index, PORTS_ANALOG_PIN pin, PORTS_PIN_MODE mode)
uint32_t DRV_TMR0_PeriodValueGet(void)
void SYS_PORTS_RemapInput(PORTS_MODULE_ID index, PORTS_REMAP_INPUT_FUNCTION function, PORTS_REMAP_INPUT_PIN remapPin)
bool PLIB_USART_ExistsReceiverAddressDetect(USART_MODULE_ID index)
void PLIB_PORTS_CnPinsEnable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
void PLIB_DMA_ChannelXEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
PORTS_CHANGE_NOTICE_METHOD PLIB_PORTS_ChannelChangeNoticeMethodGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_USART_TransmitterByteSend(USART_MODULE_ID index, int8_t data)
void SYS_PORTS_RemapOutput(PORTS_MODULE_ID index, PORTS_REMAP_OUTPUT_FUNCTION function, PORTS_REMAP_OUTPUT_PIN remapPin)
bool PLIB_DMA_ExistsChannelXSourceStartAddress(DMA_MODULE_ID index)
bool PLIB_USART_ReceiverFramingErrorHasOccurred(USART_MODULE_ID index)
void PLIB_DMA_AbortTransferSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_PORTS_ExistsPinModePerPort(PORTS_MODULE_ID index)
void SYS_PORTS_ChangeNotificationGlobalEnable(PORTS_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXStartIRQ(DMA_MODULE_ID index)
uint8_t Get_CRC_Value(void)
SYS_DMA_ERROR SYS_DMA_ChannelErrorGet(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_USART_AddressSet(USART_MODULE_ID index, uint8_t address)
void DRV_USART0_Close(void)
bool PLIB_PORTS_ExistsChangeNoticePerPortTurnOn(PORTS_MODULE_ID index)
bool PLIB_SPI_ExistsFrameErrorStatus(SPI_MODULE_ID index)
static void Decode_Manchester(void)
void PLIB_PORTS_ChangeNoticeInIdlePerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_PORTS_PinToggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void DRV_TMR4_CounterValueSet(uint32_t value)
void SYS_PORTS_ChangeNotificationPullUpEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
bool PLIB_PORTS_ExistsPortsOpenDrain(PORTS_MODULE_ID index)
void SYS_PORTS_ChangeNotificationDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void PLIB_USART_ReceiverAddressDetectEnable(USART_MODULE_ID index)
DRV_SPI_BUFFER_TYPE bufferType
uintptr_t DRV_USART_BUFFER_HANDLE
#define commands_65zzopen
size_t DRV_USART_BufferProcessedSizeGet(DRV_USART_BUFFER_HANDLE bufferHandle)
void PLIB_USART_RunInSleepModeDisable(USART_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXPatternIgnore(DMA_MODULE_ID index)
void PLIB_PORTS_CnPinsPullUpEnable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
bool DRV_TMR4_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
void SYS_DMA_ChannelTransferAdd(SYS_DMA_CHANNEL_HANDLE handle, const void *srcAddr, size_t srcSize, const void *destAddr, size_t destSize, size_t cellSize)
static void Send_Space(void)
void DRV_TMR2_Initialize(void)
static void Execute_Auto_Protocol_A(void)
void PLIB_USART_AddressMaskSet(USART_MODULE_ID index, uint8_t mask)
static SYS_STATUS DRV_TMR0_Status(void)
void PLIB_SPI_StopInIdleDisable(SPI_MODULE_ID index)
void DRV_TMR0_StopInIdleDisable(void)
bool PLIB_SPI_ExistsReceiveFIFOStatus(SPI_MODULE_ID index)
static int qqqqbmselwidth
unsigned int DRV_USART_TransmitBufferSizeGet(const DRV_HANDLE handle)
bool PLIB_DMA_ExistsCRCBitOrder(DMA_MODULE_ID index)
uint32_t DRV_IC0_Capture32BitDataRead(void)
bool PLIB_USART_ExistsReceiverAddressAutoDetect(USART_MODULE_ID index)
void PLIB_USART_TransmitterInterruptModeSelect(USART_MODULE_ID index, USART_TRANSMIT_INTR_MODE fifolevel)
size_t DRV_USART_BufferCompletedBytesGet(DRV_USART_BUFFER_HANDLE bufferHandle)
void DRV_TMR4_StopInIdleDisable(void)
void PLIB_DMA_StopInIdleEnable(DMA_MODULE_ID index)
uint32_t DRV_TMR3_CounterFrequencyGet(void)
bool PLIB_PORTS_ExistsChangeNoticePullUpPerPort(PORTS_MODULE_ID index)
void PLIB_SPI_SlaveSelectDisable(SPI_MODULE_ID index)
void PLIB_PORTS_AnPinsModeSelect(PORTS_MODULE_ID index, PORTS_AN_PIN anPins, PORTS_PIN_MODE mode)
void DRV_IC0_Initialize(void)
void(* SYS_DMA_CHANNEL_TRANSFER_EVENT_HANDLER)(SYS_DMA_TRANSFER_EVENT event, SYS_DMA_CHANNEL_HANDLE handle, uintptr_t contextHandle)
bool PLIB_USART_TransmitterIsEmpty(USART_MODULE_ID index)
void PLIB_PORTS_PinOpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void DRV_USART0_TasksError(void)
bool PLIB_SPI_TransmitBufferIsEmpty(SPI_MODULE_ID index)
static SYS_STATUS DRV_TMR4_Status(void)
static void DRV_TMR3_Open(void)
size_t DRV_USART_Write(const DRV_HANDLE handle, void *buffer, const size_t numbytes)
DRV_SPI_BUFFER_EVENT_HANDLER operationStarting
void PLIB_USART_Disable(USART_MODULE_ID index)
bool DRV_TMR2_Start(void)
uint16_t DRV_IC0_Capture16BitDataRead(void)
void PLIB_USART_ReceiverOverrunErrorClear(USART_MODULE_ID index)
TMR_PRESCALE DRV_TMR0_PrescalerGet(void)
void PLIB_SPI_TransmitUnderRunStatusClear(SPI_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXDestinationPointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool PLIB_SPI_ExistsFrameSyncPulsePolarity(SPI_MODULE_ID index)
void DRV_TMR_AlarmEnable(DRV_HANDLE handle, bool enable)
void SYS_DMA_ChannelEnable(SYS_DMA_CHANNEL_HANDLE handle)
static void Send_Message_Tasks(void)
void PLIB_DMA_ChannelXNullWriteModeDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void SYS_DEBUG_ErrorLevelSet(SYS_ERROR_LEVEL level)
void SYS_DMA_TasksError(SYS_MODULE_OBJ object)
void(* DRV_TMR_CALLBACK)(uintptr_t context, uint32_t alarmCount)
bool PLIB_DMA_ExistsSuspend(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXDisabled(DMA_MODULE_ID index)
void PLIB_SPI_PinEnable(SPI_MODULE_ID index, SPI_PIN pin)
uint32_t PLIB_DMA_RecentAddressAccessed(DMA_MODULE_ID index)
void PLIB_DMA_ChannelXOperatingTransferModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRANSFER_MODE channeltransferMode)
static void MAN_PROCESS_Tasks(void)
int32_t DRV_SPI_ClientConfigure(DRV_HANDLE handle, const DRV_SPI_CLIENT_DATA *cfgData)
void PLIB_DMA_ChannelXStartIRQSet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRIGGER_SOURCE IRQnum)
bool PLIB_USART_ReceiverIsIdle(USART_MODULE_ID index)
void PLIB_DMA_CRCWriteByteOrderAlter(DMA_MODULE_ID index)
bool DRV_TMR2_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
bool PLIB_DMA_ExistsChannelXBusy(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsCRCType(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXDestinationPointer(DMA_MODULE_ID index)
bool PLIB_SPI_ExistsAudioErrorControl(SPI_MODULE_ID index)
void qqqtotalupload(void)
static void store_switches(void)
static int qqqstructzzopen
SYS_MODULE_OBJ SYS_DEBUG_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
bool PLIB_DMA_ExistsAbortTransfer(DMA_MODULE_ID index)
bool PLIB_PORTS_ExistsPortsDirection(PORTS_MODULE_ID index)
SPI_FRAME_PULSE_EDGE framePulseEdge
bool PLIB_SPI_ExistsAudioProtocolMode(SPI_MODULE_ID index)
void PLIB_DMA_BusyActiveReset(DMA_MODULE_ID index)
bool PLIB_USART_ExistsReceiverIdleStatus(USART_MODULE_ID index)
void PLIB_PORTS_ChangeNoticePullUpPerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_DMA_ChannelXSourceSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t sourceSize)
void PLIB_DMA_ChannelXAutoDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_ChannelXAutoEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
static const uint8_t Xmit11[312]
static void qqoutput4(FILEPOINT char *s, int i, int j, int k, int l)
bool PLIB_USART_ExistsEnable(USART_MODULE_ID index)
bool PLIB_USART_ExistsModuleBusyStatus(USART_MODULE_ID index)
bool PLIB_SPI_ExistsErrorInterruptControl(SPI_MODULE_ID index)
void PLIB_PORTS_Toggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK toggleMask)
void SYS_DMA_ChannelResume(SYS_DMA_CHANNEL_HANDLE handle)
TMR_PRESCALE DRV_TMR1_PrescalerGet(void)
void PLIB_PORTS_PinOpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
static void Execute_System(void)
bool PLIB_USART_ExistsTransmitterEnable(USART_MODULE_ID index)
TMR_PRESCALE DRV_TMR4_PrescalerGet(void)
bool PLIB_DMA_ChannelXAutoIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_DMA_ChannelXCollisionStatus(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_COLLISION collisonType)
bool PLIB_USART_ExistsReceiverDataAvailableStatus(USART_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticePullDownDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
static void qqoutput2(FILEPOINT char *s, int i, int j)
uint32_t DRV_IC_Capture32BitDataRead(DRV_HANDLE handle)
static DRV_TMR_OPERATION_MODE DRV_TMR2_OperationModeGet(void)
bool SYS_DMA_IsBusy(void)
uint16_t PLIB_DMA_ChannelXSourceSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
uint32_t DRV_TMR_CounterValueGet(DRV_HANDLE handle)
bool PLIB_SPI_ReadDataIsSignExtended(SPI_MODULE_ID index)
uintptr_t DRV_USART_BUFFER_HANDLE
void PLIB_DMA_ChannelXChainEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
DRV_USART_CLIENT_STATUS DRV_USART0_ClientStatus(void)
void PLIB_DMA_ChannelXDataSizeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_DATA_SIZE channelDataSize)
static void qqbmsoutput(FILEPOINT char *s, unsigned int i)
void SYS_DMA_Tasks(SYS_MODULE_OBJ object, DMA_CHANNEL activeChannel)
bool DRV_TMR3_Start(void)
uint32_t DRV_TMR4_CounterFrequencyGet(void)
void DRV_TMR_CounterValueSet(DRV_HANDLE handle, uint32_t counterPeriod)
void PLIB_USART_BaudRateSet(USART_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
void DRV_TMR0_PeriodValueSet(uint32_t value)
bool PLIB_SPI_ExistsEnableControl(SPI_MODULE_ID index)
void SYS_PORTS_PinDirectionSelect(PORTS_MODULE_ID index, SYS_PORTS_PIN_DIRECTION pinDir, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_PORTS_ChannelChangeNoticeMethodSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_CHANGE_NOTICE_METHOD changeNoticeMethod)
void PLIB_PORTS_ChangeNoticePullUpDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void PLIB_DMA_ChannelXPatternIgnoreSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint8_t pattern)
void PLIB_USART_LoopbackEnable(USART_MODULE_ID index)
void PLIB_SPI_FIFODisable(SPI_MODULE_ID index)
bool DRV_ADC_SamplesAvailable(uint8_t bufIndex)
void PLIB_PORTS_PinDirectionInputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_DMA_ExistsCRCData(DMA_MODULE_ID index)
DRV_HANDLE DRV_SPI_Open(const SYS_MODULE_INDEX drvIndex, const DRV_IO_INTENT ioIntent)
void PLIB_SPI_SlaveSelectEnable(SPI_MODULE_ID index)
bool PLIB_SPI_ExistsBaudRateClock(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXINTSourceFlagSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
void APP_Initialize(void)
DRV_SPI_BUFFER_EVENT_HANDLER operationEnded
uint32_t DRV_TMR_AlarmPeriodGet(DRV_HANDLE handle)
void PLIB_DMA_ChannelXPatternIgnoreByteEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ExistsReceiverAddressMask(USART_MODULE_ID index)
void * PLIB_USART_ReceiverAddressGet(USART_MODULE_ID index)
void PLIB_DMA_ChannelXDestinationSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t destinationSize)
CLK_BUSES_PERIPHERAL spiClk
void(* ldra_void_function)()
DRV_TMR_CLIENT_STATUS DRV_TMR0_ClientStatus(void)
void DRV_USART_ByteReceiveCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
uint8_t DRV_PMP0_Read(void)
void Generate_Sine_Wave_Data(float32_t NoOfTicks)
void PLIB_SPI_PinDisable(SPI_MODULE_ID index, SPI_PIN pin)
uint16_t PLIB_DMA_ChannelXPatternDataGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool PLIB_SPI_ExistsFIFOShiftRegisterEmptyStatus(SPI_MODULE_ID index)
static DRV_TMR_OPERATION_MODE DRV_TMR1_OperationModeGet(void)
static void Check_WL_CPS_Over_Current(void)
void PLIB_SPI_SlaveEnable(SPI_MODULE_ID index)
void PLIB_USART_InitializeOperation(USART_MODULE_ID index, USART_RECEIVE_INTR_MODE receiveInterruptMode, USART_TRANSMIT_INTR_MODE transmitInterruptMode, USART_OPERATION_MODE operationMode)
void DRV_TMR4_CounterClear(void)
void PLIB_SPI_BufferWrite(SPI_MODULE_ID index, uint8_t data)
uint8_t PLIB_SPI_FIFOCountGet(SPI_MODULE_ID index, SPI_FIFO_TYPE type)
void PLIB_SPI_FramedCommunicationEnable(SPI_MODULE_ID index)
unsigned int DRV_USART0_ReceiverBufferSizeGet(void)
SPI_COMMUNICATION_WIDTH commWidth
void PLIB_USART_RunInSleepModeEnable(USART_MODULE_ID index)
bool PLIB_USART_ExistsReceiver9Bits(USART_MODULE_ID index)
void DRV_USART_Deinitialize(SYS_MODULE_OBJ object)
void PLIB_SPI_OutputDataPhaseSelect(SPI_MODULE_ID index, SPI_OUTPUT_DATA_PHASE phase)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddRead2(DRV_HANDLE handle, void *rxBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
void PLIB_PORTS_ChangeNoticeDisable(PORTS_MODULE_ID index)
bool DRV_TMR0_Start(void)
bool PLIB_SPI_ExistsBaudRate(SPI_MODULE_ID index)
void SYS_DMA_ChannelSetup(SYS_DMA_CHANNEL_HANDLE handle, SYS_DMA_CHANNEL_OP_MODE modeEnable, DMA_TRIGGER_SOURCE eventSrc)
void PLIB_PORTS_RemapInput(PORTS_MODULE_ID index, PORTS_REMAP_INPUT_FUNCTION inputFunction, PORTS_REMAP_INPUT_PIN remapInputPin)
bool PLIB_SPI_ExistsFrameSyncPulseCounter(SPI_MODULE_ID index)
uint32_t DRV_TMR_CounterFrequencyGet(DRV_HANDLE handle)
void PLIB_USART_TransmitterDisable(USART_MODULE_ID index)
void DRV_TMR_Tasks(SYS_MODULE_OBJ object)
bool PLIB_PORTS_ExistsChangeNoticeEdgeControl(PORTS_MODULE_ID index)
void PLIB_SPI_FrameSyncPulseEdgeSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_EDGE edge)
bool DRV_TMR3_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
void PLIB_DMA_ChannelXBusyActiveSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_DMA_ExistsCRCAppendMode(DMA_MODULE_ID index)
bool PLIB_SPI_ExistsTransmitUnderRunStatus(SPI_MODULE_ID index)
void PLIB_PORTS_PinChangeNoticePerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
static void DRV_TMR3_DeInitialize(void)
void SYS_PORTS_PinPullDownDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DRV_USART_CLIENT_STATUS DRV_USART_ClientStatus(DRV_HANDLE handle)
bool PLIB_PORTS_ExistsPinChangeNotice(PORTS_MODULE_ID index)
void PLIB_DMA_Disable(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsChannelX(DMA_MODULE_ID index)
void SYS_DMA_TasksErrorISR(SYS_MODULE_OBJ object, DMA_CHANNEL activeChannel)
bool PLIB_SPI_TransmitBufferIsFull(SPI_MODULE_ID index)
static void DRV_TMR2_DeInitialize(void)
bool PLIB_DMA_LastBusAccessIsRead(DMA_MODULE_ID index)
DRV_HANDLE DRV_TMR_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT intent)
void PLIB_PORTS_ChannelSlewRateSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK channelMask, PORTS_PIN_SLEW_RATE slewRate)
void PLIB_SPI_BufferClear(SPI_MODULE_ID index)
void PLIB_USART_StopInIdleEnable(USART_MODULE_ID index)
bool PLIB_SPI_ExistsTransmitBufferFullStatus(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXPrioritySelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_PRIORITY channelPriority)
static void DRV_TMR0_Tasks(void)
bool PLIB_SPI_ExistsFramedCommunication(SPI_MODULE_ID index)
uint32_t DRV_TMR2_PeriodValueGet(void)
bool PLIB_DMA_ExistsCRCXOREnable(DMA_MODULE_ID index)
SYS_PORTS_PULLUP_PULLDOWN_STATUS
bool PLIB_PORTS_ExistsChangeNoticeInIdle(PORTS_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticePullUpEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_USART_ExistsBaudRateAutoDetect(USART_MODULE_ID index)
void DRV_TMR3_StopInIdleEnable(void)
void PLIB_SPI_Enable(SPI_MODULE_ID index)
void PLIB_USART_ReceiverDisable(USART_MODULE_ID index)
uint8_t PLIB_USART_AddressMaskGet(USART_MODULE_ID index)
DRV_USART_TRANSFER_STATUS
void SYS_PORTS_PinPullDownEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_USART_BaudRateHighSet(USART_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
bool PLIB_PORTS_ExistsChannelChangeNoticeMethod(PORTS_MODULE_ID index)
void PLIB_SPI_MasterEnable(SPI_MODULE_ID index)
void PLIB_PORTS_OpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
uint8_t Calc_CRC_Uplink(uint16_t Count, const uint8_t Bytes [])
void Adjust_WL_CPS_Voltage(uint8_t target)
DMA_DESTINATION_ADDRESSING_MODE PLIB_DMA_ChannelXDestinationAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint8_t Calc_CRC_Array(uint16_t Count, const uint8_t Bytes [])
static void DRV_TMR4_Close(void)
uint16_t PLIB_DMA_ChannelXDestinationSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool PLIB_PORTS_ExistsChangeNoticePullDownPerPort(PORTS_MODULE_ID index)
static float32_t Calc_Fsk_Scaling(void)
DMA_CHANNEL_ADDRESSING_MODE PLIB_DMA_ChannelXAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
SYS_ERROR_LEVEL SYS_DEBUG_ErrorLevelGet(void)
void DRV_TMR_CounterClear(DRV_HANDLE handle)
bool PLIB_SPI_ExistsFrameSyncPulseEdge(SPI_MODULE_ID index)
SYS_STATUS SYS_DEBUG_Status(SYS_MODULE_OBJ object)
DRV_TMR_CLIENT_STATUS DRV_TMR4_ClientStatus(void)
bool PLIB_USART_ExistsReceiverOverrunStatus(USART_MODULE_ID index)
DRV_SPI_BUFFER_EVENT_HANDLER operationEnded
uint16_t DRV_IC_Capture16BitDataRead(DRV_HANDLE handle)
DRV_TMR_CLIENT_STATUS DRV_TMR3_ClientStatus(void)
void DRV_USART_TasksReceive(SYS_MODULE_OBJ object)
bool GetDepthStatus(void)
bool PLIB_DMA_ExistsChannelXPatternIgnoreByte(DMA_MODULE_ID index)
void DRV_TMR_AlarmDeregister(DRV_HANDLE handle)
void PLIB_PORTS_ChangeNoticeInIdlePerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool DRV_IC_BufferIsEmpty(DRV_HANDLE handle)
void DRV_TMR3_PeriodValueSet(uint32_t value)
void DRV_USART_BufferAddWrite(const DRV_HANDLE handle, DRV_USART_BUFFER_HANDLE *bufferHandle, void *buffer, const size_t size)
static void qqoutput(FILEPOINT char *s, int i)
void PLIB_SPI_AudioTransmitModeSelect(SPI_MODULE_ID index, SPI_AUDIO_TRANSMIT_MODE mode)
DRV_USART_TRANSFER_STATUS DRV_USART_TransferStatus(const DRV_HANDLE handle)
uint8_t PLIB_SPI_BufferRead(SPI_MODULE_ID index)
void DRV_TMR3_StopInIdleDisable(void)
bool PLIB_DMA_ChannelXReloadIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWriteRead(DRV_HANDLE handle, void *txBuffer, size_t txSize, void *rxBuffer, size_t rxSize, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
bool PLIB_PORTS_ExistsChangeNoticePerPortInIdle(PORTS_MODULE_ID index)
DRV_TMR_OPERATION_MODE DRV_TMR_DividerRangeGet(DRV_HANDLE handle, DRV_TMR_DIVIDER_RANGE *pDivRange)
static int commands_65zqqzqz(qqnull_params)
void Prepare_Dwn_Msg(uint8_t Identifier, uint8_t Cmd, uint8_t Msg_Length)
PORTS_DATA_TYPE SYS_PORTS_InterruptStatusGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_USART_ExistsLoopback(USART_MODULE_ID index)
DRV_USART_ERROR DRV_USART0_ErrorGet(void)
bool DRV_USART0_TransmitBufferIsFull(void)
uint32_t DRV_TMR2_CounterValueGet(void)
void DRV_PMP0_ModeConfig(void)
DRV_USART_BUFFER_RESULT DRV_USART_BufferRemove(DRV_USART_BUFFER_HANDLE bufferHandle)
DRV_TMR_CLIENT_STATUS DRV_TMR_ClientStatus(DRV_HANDLE handle)
void PLIB_PORTS_ChannelChangeNoticeEdgeEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK edgeRisingMask, PORTS_DATA_MASK edgeFallingMask)
static void DRV_TMR0_DeInitialize(void)
void PLIB_DMA_ChannelXReloadDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint16_t PLIB_DMA_ChannelXCellProgressPointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
SYS_MODULE_OBJ SYS_DMA_Initialize(const SYS_MODULE_INIT *const init)
static DRV_TMR_OPERATION_MODE DRV_TMR4_OperationModeGet(void)
bool PLIB_USART_ExistsTransmitter9BitsSend(USART_MODULE_ID index)
bool PLIB_DMA_ExistsBusy(DMA_MODULE_ID index)
void PLIB_SPI_ClockPolaritySelect(SPI_MODULE_ID index, SPI_CLOCK_POLARITY polarity)
struct _DRV_SPI_CLIENT_DATA DRV_SPI_CLIENT_DATA
bool DRV_TMR_ClockSet(DRV_HANDLE handle, DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE preScale)
bool PLIB_DMA_CRCAppendModeIsEnabled(DMA_MODULE_ID index)
PORTS_DATA_TYPE PLIB_PORTS_Read(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_USART_ExistsReceiverInterruptMode(USART_MODULE_ID index)
void DRV_SPI_Tasks(SYS_MODULE_OBJ object)
void DRV_USART_ByteErrorCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
static void DRV_TMR1_Close(void)
void DRV_TMR0_StopInIdleEnable(void)
bool PLIB_SPI_ExistsReceiveBufferStatus(SPI_MODULE_ID index)
bool PLIB_SPI_ExistsBuffer(SPI_MODULE_ID index)
void PLIB_SPI_FrameSyncPulsePolaritySelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_POLARITY polarity)
void PLIB_DMA_ChannelXChainToHigher(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_ChannelXDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsClockPolarity(SPI_MODULE_ID index)
static void qqoutput3(FILEPOINT char *s, int i, int j, int k)
void DRV_USART_TasksTransmit(SYS_MODULE_OBJ object)
void DRV_TMR2_CounterValueSet(uint32_t value)
bool DRV_TMR0_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
void DRV_TMR2_CounterClear(void)
void DRV_TMR1_PeriodValueSet(uint32_t value)
void PLIB_PORTS_ChannelModeSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK modeMask, PORTS_PIN_MODE mode)
bool PLIB_USART_ExistsLineControlMode(USART_MODULE_ID index)
static void DRV_TMR4_DeInitialize(void)
void DRV_USART_WriteByte(const DRV_HANDLE handle, const uint8_t byte)
void DRV_USART_TasksError(SYS_MODULE_OBJ object)
DRV_HANDLE DRV_USART_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT ioIntent)
void DRV_TMR2_StopInIdleEnable(void)
uint16_t current_array[5]
SPI_INPUT_SAMPLING_PHASE inputSamplePhase
void SYS_PORTS_DirectionSelect(PORTS_MODULE_ID index, SYS_PORTS_PIN_DIRECTION pinDir, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_PORTS_ChannelChangeNoticeEdgeDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK edgeRisingMask, PORTS_DATA_MASK edgeFallingMask)
SYS_ERROR_LEVEL gblErrLvl
unsigned int DRV_USART0_TransmitBufferSizeGet(void)
void PLIB_PORTS_Write(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value)
DRV_SPI_BUFFER_EVENT_HANDLER operationStarting
void PLIB_SPI_BaudRateSet(SPI_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
void SYS_DEBUG_Tasks(SYS_MODULE_OBJ object)
bool DRV_TMR_Start(DRV_HANDLE handle)
void SYS_DEBUG_Deinitialize(SYS_MODULE_OBJ object)
void PLIB_DMA_ChannelXINTSourceEnable(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
void PLIB_SPI_AudioProtocolDisable(SPI_MODULE_ID index)
void PLIB_SPI_InputSamplePhaseSelect(SPI_MODULE_ID index, SPI_INPUT_SAMPLING_PHASE phase)
void PLIB_USART_ReceiverEnable(USART_MODULE_ID index)
void Prepare_Return_A(uint8_t byte, uint16_t data2, uint16_t data1)
void PLIB_USART_TransmitterIdleIsLowDisable(USART_MODULE_ID index)
void PLIB_DMA_StopInIdleDisable(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsCRCByteOrder(DMA_MODULE_ID index)
DMA_CRC_TYPE PLIB_DMA_CRCTypeGet(DMA_MODULE_ID index)
void PLIB_SPI_FrameSyncPulseCounterSelect(SPI_MODULE_ID index, SPI_FRAME_SYNC_PULSE pulse)
void SYS_PORTS_OpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_DMA_SuspendDisable(DMA_MODULE_ID index)
bool PLIB_DMA_ChannelXBufferedDataIsWritten(DMA_MODULE_ID index, DMA_CHANNEL channel)
static void Read_WL_CPS_V_I(void)
bool PLIB_USART_ExistsBaudRateHigh(USART_MODULE_ID index)
static const uint8_t Xmit00[168]
void PLIB_SPI_FIFOEnable(SPI_MODULE_ID index)
DRV_USART_BAUD_SET_RESULT DRV_USART0_BaudSet(uint32_t baud)
bool PLIB_SPI_Exists16bitBuffer(SPI_MODULE_ID index)
void PLIB_SPI_Disable(SPI_MODULE_ID index)
void SYS_DMA_ChannelSuspend(SYS_DMA_CHANNEL_HANDLE handle)
PORTS_DATA_MASK PLIB_PORTS_DirectionGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
SPI_AUDIO_TRANSMIT_MODE audioTransmitMode
void PLIB_DMA_ChannelXBusyInActiveSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
PORTS_DATA_TYPE SYS_PORTS_Read(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
static void Test_Manchester(void)
bool PLIB_USART_ExistsReceiverIdleStateLowEnable(USART_MODULE_ID index)
DRV_USART_BAUD_SET_RESULT
uintptr_t DRV_SPI_BUFFER_HANDLE
void DRV_ADC_DeInitialize(void)
DRV_TMR_OPERATION_MODE DRV_TMR4_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
void PLIB_USART_ReceiverInterruptModeSelect(USART_MODULE_ID index, USART_RECEIVE_INTR_MODE interruptMode)
void SYS_PORTS_Clear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK clearMask)
DRV_USART_ERROR DRV_USART_ErrorGet(const DRV_HANDLE client)
void DRV_TMR2_PeriodValueSet(uint32_t value)
void PLIB_PORTS_PinModePerPortSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_PIN_MODE mode)
bool PLIB_DMA_ExistsChannelXTrigger(DMA_MODULE_ID index)
SPI_AUDIO_PROTOCOL audioProtocolMode
void PLIB_DMA_CRCBitOrderSelect(DMA_MODULE_ID index, DMA_CRC_BIT_ORDER bitOrder)
void PLIB_DMA_ChannelXPeripheralAddressSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t peripheraladdress)
bool PLIB_USART_ReceiverAddressIsReceived(USART_MODULE_ID index)
bool PLIB_SPI_ExistsCommunicationWidth(SPI_MODULE_ID index)
static void Package_Manchester(void)
DRV_SPI_CLOCK_MODE clockMode
void PLIB_DMA_CRCDataWrite(DMA_MODULE_ID index, uint32_t DMACRCdata)
static void DRV_TMR3_Close(void)
bool PLIB_SPI_TransmitUnderRunStatusGet(SPI_MODULE_ID index)
uint32_t PLIB_DMA_ChannelXDestinationStartAddressGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
TMR_PRESCALE DRV_TMR2_PrescalerGet(void)
bool PLIB_USART_ExistsTransmitterEmptyStatus(USART_MODULE_ID index)
size_t DRV_USART_Read(const DRV_HANDLE handle, void *buffer, const size_t numbytes)
bool PLIB_DMA_SuspendIsEnabled(DMA_MODULE_ID index)
bool PLIB_DMA_ChannelXIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
void * PLIB_USART_TransmitterAddressGet(USART_MODULE_ID index)
bool PLIB_PORTS_PinChangeNoticeEdgeIsEnabled(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_CHANGE_NOTICE_EDGE cnEdgeType)
SYS_MODULE_OBJ DRV_TMR_Initialize(const SYS_MODULE_INDEX drvIndex, const SYS_MODULE_INIT *const init)
void SYS_PORTS_Set(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value, PORTS_DATA_MASK mask)
void PLIB_USART_BaudRateHighDisable(USART_MODULE_ID index)
uint8_t PLIB_USART_AddressGet(USART_MODULE_ID index)
uintptr_t SYS_DMA_CHANNEL_HANDLE
DMA_CHANNEL PLIB_DMA_CRCChannelGet(DMA_MODULE_ID index)
bool PLIB_USART_ExistsReceiver(USART_MODULE_ID index)
DMA_CRC_BYTE_ORDER PLIB_DMA_CRCByteOrderGet(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXEvent(DMA_MODULE_ID index)
bool PLIB_PORTS_ExistsPortsWrite(PORTS_MODULE_ID index)
void Set_WL_SPS_CurrentLimit(uint16_t value)
bool PLIB_USART_ReceiverParityErrorHasOccurred(USART_MODULE_ID index)
static COMMAND_STATES CMD_STATES
void(* DRV_SPI_BUFFER_EVENT_HANDLER)(DRV_SPI_BUFFER_EVENT event, DRV_SPI_BUFFER_HANDLE bufferHandle, void *context)
SYS_MODULE_OBJ DRV_USART0_Initialize(void)
static void DRV_TMR1_Tasks(void)
size_t SYS_DMA_ChannelSourceTransferredSizeGet(SYS_DMA_CHANNEL_HANDLE handle)
static void read_switches(void)
DRV_USART_BAUD_SET_RESULT DRV_USART_BaudSet(const DRV_HANDLE client, uint32_t baud)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWriteRead2(DRV_HANDLE handle, void *txBuffer, size_t txSize, void *rxBuffer, size_t rxSize, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
bool PLIB_PORTS_PinChangeNoticeEdgeHasOccurred(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void DRV_ADC_Initialize(void)
bool PLIB_DMA_ChannelXTriggerIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
void PLIB_USART_BRGClockSourceSelect(USART_MODULE_ID index, USART_BRG_CLOCK_SOURCE brgClockSource)
void PLIB_USART_BaudRateHighEnable(USART_MODULE_ID index)
SYS_DMA_CHANNEL_CHAIN_PRIO
void Reset_CRC_Value(void)
void PLIB_PORTS_Set(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value, PORTS_DATA_MASK mask)
void PLIB_USART_IrDAEnable(USART_MODULE_ID index)
bool PLIB_DMA_ExistsChannelBits(DMA_MODULE_ID index)
void SYS_PORTS_PinWrite(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, bool value)
INT_SOURCE rxInterruptSource
void DRV_TMR0_Initialize(void)
int16_t PLIB_USART_Receiver9BitsReceive(USART_MODULE_ID index)
void PLIB_SPI_AudioErrorEnable(SPI_MODULE_ID index, SPI_AUDIO_ERROR error)
void PLIB_PORTS_PinDirectionOutputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_DMA_CRCAppendModeDisable(DMA_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXStartAddressOffsetGet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_ADDRESS_OFFSET_TYPE offset)
DRV_TMR_OPERATION_MODE DRV_TMR_OperationModeGet(DRV_HANDLE handle)
void DRV_IC_Stop(DRV_HANDLE handle)
DMA_CHANNEL_TRANSFER_DIRECTION PLIB_DMA_ChannelXTransferDirectionGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
PORTS_DATA_TYPE PLIB_PORTS_ReadLatched(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_USART_HandshakeModeSelect(USART_MODULE_ID index, USART_HANDSHAKE_MODE handshakeConfig)
static void Flush_Buffer_Manchester(void)
void DRV_TMR_Close(DRV_HANDLE handle)
void PLIB_SPI_StopInIdleEnable(SPI_MODULE_ID index)
void PLIB_USART_TransmitterEnable(USART_MODULE_ID index)
void PLIB_DMA_CRCPolynomialLengthSet(DMA_MODULE_ID index, uint8_t polyLength)
bool PLIB_USART_ExistsTransmitterIdleIsLow(USART_MODULE_ID index)
void PLIB_DMA_ChannelXCellSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t CellSize)
void PLIB_PORTS_PinWrite(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, bool value)
bool DRV_TMR_AlarmRegister(DRV_HANDLE handle, uint32_t divider, bool isPeriodic, uintptr_t context, DRV_TMR_CALLBACK callBack)
bool PLIB_USART_ExistsWakeOnStart(USART_MODULE_ID index)
bool PLIB_SPI_ExistsBusStatus(SPI_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNotice(PORTS_MODULE_ID index)
uint32_t DRV_TMR3_PeriodValueGet(void)
bool PLIB_DMA_ExistsChannelXPriority(DMA_MODULE_ID index)
void SYS_PORTS_ChangeNotificationGlobalDisable(PORTS_MODULE_ID index)
void(* DRV_USART_BUFFER_EVENT_HANDLER)(DRV_USART_BUFFER_EVENT event, DRV_USART_BUFFER_HANDLE bufferHandle, uintptr_t context)
void DRV_SPI_Deinitialize(SYS_MODULE_OBJ object)
void PLIB_DMA_ChannelXDisabledDisablesEvents(DMA_MODULE_ID index, DMA_CHANNEL channel)
SYS_STATUS DRV_USART_Status(SYS_MODULE_OBJ object)
bool PLIB_USART_ExistsTransmitterBufferFullStatus(USART_MODULE_ID index)
DRV_USART_LINE_CONTROL_SET_RESULT DRV_USART0_LineControlSet(DRV_USART_LINE_CONTROL lineControlMode)
INT_SOURCE errInterruptSource
void DRV_PMP0_Initialize(void)
void PLIB_PORTS_ChangeNoticePullDownPerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_SPI_ExistsSlaveSelectControl(SPI_MODULE_ID index)
DRV_TMR_CLIENT_STATUS DRV_TMR1_ClientStatus(void)
void PLIB_DMA_SuspendEnable(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsLastBusAccess(DMA_MODULE_ID index)
ldra_void_function qqqaccumreset[QQQnumfil]
bool PLIB_DMA_ExistsChannelXPatternLength(DMA_MODULE_ID index)
void PLIB_USART_ReceiverIdleStateLowEnable(USART_MODULE_ID index)
void PLIB_DMA_ChannelXTriggerDisable(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
static SYS_STATUS DRV_TMR1_Status(void)
static int commands_65zqzqzq(int qqqi)
void SYS_PORTS_PinToggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_USART_StopInIdleDisable(USART_MODULE_ID index)
bool PLIB_SPI_ExistsInputSamplePhase(SPI_MODULE_ID index)
bool PLIB_DMA_CRCIsEnabled(DMA_MODULE_ID index)
void PLIB_SPI_BufferWrite16bit(SPI_MODULE_ID index, uint16_t data)
static void DRV_TMR3_Tasks(void)
uint16_t PLIB_DMA_ChannelXCellSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool SYS_DMA_ChannelIsBusy(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_PORTS_ExistsChangeNoticeEdgeStatus(PORTS_MODULE_ID index)
bool DRV_TMR_GateModeClear(DRV_HANDLE handle)
bool PLIB_DMA_ExistsChannelXChain(DMA_MODULE_ID index)
uint32_t DRV_TMR4_CounterValueGet(void)
bool DRV_USART_ReceiverBufferIsEmpty(const DRV_HANDLE handle)
bool PLIB_SPI_ExistsAudioCommunicationWidth(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsEnableControl(DMA_MODULE_ID index)
static void qqqbitmapreset(qqnull_params)
DRV_TMR_OPERATION_MODE DRV_TMR3_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
void PLIB_PORTS_ChangeNoticeInIdleDisable(PORTS_MODULE_ID index)
void DRV_TMR3_CounterValueSet(uint32_t value)
void PLIB_PORTS_CnPinsDisable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
bool PLIB_SPI_Exists32bitBuffer(SPI_MODULE_ID index)
static void ValidateComm(void)
void PLIB_PORTS_PinClear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
uint8_t PLIB_DMA_CRCPolynomialLengthGet(DMA_MODULE_ID index)
static void qqqupload(qqnull_params)
void PLIB_SPI_ErrorInterruptEnable(SPI_MODULE_ID index, SPI_ERROR_INTERRUPT error)
void SYS_PORTS_PinSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_SPI_ExistsAudioProtocolControl(SPI_MODULE_ID index)
DMA_TRANSFER_MODE PLIB_DMA_ChannelXOperatingTransferModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsFIFOInterruptMode(SPI_MODULE_ID index)
DRV_SPI_TASK_MODE taskMode
DRV_TMR_CLIENT_STATUS DRV_TMR2_ClientStatus(void)
void PLIB_DMA_CRCXOREnableSet(DMA_MODULE_ID index, uint32_t DMACRCXOREnableMask)
void PLIB_DMA_ChannelXAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_ADDRESSING_MODE channelAddressMode)
void PLIB_PORTS_Clear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK clearMask)
bool DRV_TMR1_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
bool PLIB_DMA_ExistsChannelXSourcePointer(DMA_MODULE_ID index)
void SYS_PORTS_Write(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value)
bool PLIB_USART_ExistsTransmitter(USART_MODULE_ID index)
void PLIB_PORTS_ChangeNoticeInIdleEnable(PORTS_MODULE_ID index)
SYS_STATUS DRV_USART0_Status(void)
PORTS_DATA_MASK SYS_PORTS_DirectionGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void Clear_Status(uint8_t bitposn)
static void DRV_TMR0_Close(void)
bool PLIB_DMA_ExistsStopInIdle(DMA_MODULE_ID index)
bool process_complete_flag
bool PLIB_DMA_ExistsChannelXDestinationStartAddress(DMA_MODULE_ID index)
void PLIB_USART_Transmitter9BitsSend(USART_MODULE_ID index, int8_t data, bool Bit9th)
bool PLIB_USART_ExistsOperationMode(USART_MODULE_ID index)
uint8_t PLIB_DMA_ChannelBitsGet(DMA_MODULE_ID index)
bool PLIB_DMA_ChannelXPatternIgnoreByteIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
void Set_Bias(uint8_t value)
bool PLIB_USART_ReceiverOverrunHasOccurred(USART_MODULE_ID index)
bool PLIB_SPI_ExistsFrameSyncPulseDirection(SPI_MODULE_ID index)
bool PLIB_DMA_ChannelXBusyIsBusy(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool b_command_complete_flag
void PLIB_SPI_FrameSyncPulseWidthSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_WIDTH width)
bool PLIB_USART_ExistsRunInOverflow(USART_MODULE_ID index)
void SYS_DMA_Resume(void)
void PLIB_DMA_ChannelXTransferCountSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t transferCount)
DMA_CHANNEL_PRIORITY PLIB_DMA_ChannelXPriorityGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint32_t SYS_DMA_ChannelCRCGet(void)
void PLIB_SPI_AudioErrorDisable(SPI_MODULE_ID index, SPI_AUDIO_ERROR error)
bool PLIB_DMA_ChannelXINTSourceFlagGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
void PLIB_PORTS_PinChangeNoticeDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
void PLIB_DMA_StartTransferSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
uintptr_t SYS_DMA_CHANNEL_HANDLE
void DRV_TMR1_Initialize(void)
bool PLIB_DMA_ExistsChannelXINTSourceFlag(DMA_MODULE_ID index)
bool PLIB_SPI_ExistsReceiverOverflow(SPI_MODULE_ID index)
void DRV_TMR4_StopInIdleEnable(void)
uint32_t DRV_TMR2_CounterFrequencyGet(void)
TMR_PRESCALE DRV_TMR_PrescalerGet(DRV_HANDLE handle)
bool DRV_TMR_AlarmDisable(DRV_HANDLE handle)
SPI_FRAME_SYNC_PULSE frameSyncPulse
bool DRV_USART_TransmitBufferIsFull(const DRV_HANDLE handle)
void DRV_USART0_TasksReceive(void)
bool PLIB_DMA_ExistsCRCWriteByteOrder(DMA_MODULE_ID index)
bool PLIB_DMA_IsBusy(DMA_MODULE_ID index)
void PLIB_USART_ReceiverIdleStateLowDisable(USART_MODULE_ID index)
bool PLIB_SPI_ExistsReadDataSignStatus(SPI_MODULE_ID index)
void PLIB_USART_ReceiverAddressAutoDetectDisable(USART_MODULE_ID index)
void SYS_PORTS_PinOpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_SPI_ReceiverBufferIsFull(SPI_MODULE_ID index)
void PLIB_PORTS_PinChangeNoticePerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_DMA_ChannelXPatternLengthSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_PATTERN_LENGTH patternLen)
static int commands_65zqendz(int qqqi)
void Set_HVPS_Ramp_Rate(uint16_t value)
bool PLIB_SPI_ExistsMasterControl(SPI_MODULE_ID index)
void SYS_PORTS_PinOpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_DMA_ExistsChannelXCellSize(DMA_MODULE_ID index)
DRV_TMR_OPERATION_MODE DRV_TMR2_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
void PLIB_PORTS_PinSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void SYS_DMA_ChannelForceStart(SYS_DMA_CHANNEL_HANDLE handle)
uint32_t DRV_TMR_AlarmHasElapsed(DRV_HANDLE handle)
bool PLIB_PORTS_ExistsChangeNoticePullUp(PORTS_MODULE_ID index)
void PLIB_DMA_ChannelXChainDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_CRCDisable(DMA_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticePullDownEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_SPI_ExistsStopInIdleControl(SPI_MODULE_ID index)